RFC: embedded Linux presentation on RISC-V

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Michael Opdenacker

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Nov 28, 2019, 9:11:03 AM11/28/19
to sw-...@groups.riscv.org
Greetings,

I recently made a presentation about embedded Linux on RISC-V, using
QEMU for experiments: https://frama.link/ZvbAu7Qo

As I'm still new to this architecture, don't hesitate to share your
comments and suggestions with me. By the way, the presentation sources
are freely available under the CC-BY-SA license, so don't hesitate to
recycle them if useful ;)

Thanks in advance,

Cheers,

Michael.

--
Michael Opdenacker, CEO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Michael Opdenacker

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Dec 18, 2019, 8:31:32 AM12/18/19
to Umit Sami, RISC-V SW Dev
Hi Umi,

Apologies for the late reply... Thanks for your appreciation!

On 11/29/19 10:34 PM, Umit Sami wrote:
> Hi Michael,
>
> I am looking for an embedded linux implementation running on risc-v
> core.  Are you able to load and run linux kernel 5.x at this point or
> still at 2.6 level?  if so, is it stable ? Great work and
> presentation. thanks for sharing.  Let's connect and chat more !


Yes, I was using mainline Linux 5.4-rc7. Except the inability to boot
with a built-in initramfs, which I will try to investigate further,
everything I tried so far as working fine.

Don't hesitate to reproduce my steps and get back to me (through this
list) if any trouble.

atish patra

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Dec 18, 2019, 4:45:14 PM12/18/19
to Michael Opdenacker, RISC-V SW Dev
Hi Michael,
Excellent presentation. You can use OpenSBI as well as M-mode run time service provider instead of BBL as well.

Few advantages:
1. OpenSBI doesn't require kernel image to be passed as payload. As a result, you don't need recompile it if you change your kernel.
2. U-Boot proper can be used as a last stage boot loader.
3. Coreboot/U-Boot SPL can be used as first stage boot loader.


The documentation in OpenSBI should be a good starting point if you have not explored it already.

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Regards,
Atish

Jorg Brown

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Dec 18, 2019, 9:36:48 PM12/18/19
to Michael Opdenacker, RISC-V SW Dev
Thanks for the presentation Michael!

One question: RISC-V is all about configurability.  But your preso just uses "riscv64".  Which 64-bit RISC-V model is that?  rv64imafdc I presume?  How would I specify a different one?

-- Jorg

On Thu, Nov 28, 2019 at 6:11 AM Michael Opdenacker <michael.o...@bootlin.com> wrote:

Billa Surendra

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Dec 19, 2019, 1:25:28 AM12/19/19
to RISC-V SW Dev
Hi Michael,


Excellent presentation for beginners, Who want to make Embedded Linux for RISC-V architecture. I want Help from you for making fedora distro from  scratch for RV64IMAFD. Please help me how to start building fedora for RISC-V. Any king of help is appreciable.

Thanks
BIlla

atish patra

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Dec 19, 2019, 3:13:46 AM12/19/19
to Billa Surendra, RISC-V SW Dev
On Wed, Dec 18, 2019 at 10:25 PM Billa Surendra <billa.i...@gmail.com> wrote:
Hi Michael,


Excellent presentation for beginners, Who want to make Embedded Linux for RISC-V architecture. I want Help from you for making fedora distro from  scratch for RV64IMAFD. Please help me how to start building fedora for RISC-V. Any king of help is appreciable.


You don't need to build a fedora distro from scratch. You just need download the prebuilt fedora rootfs image and use it in Qemu as you would have used
a rootfs generated by buildroot.

Here are some instructions

Some instructions may be out of date but you just need to get hold of the fedora rootfs image.
 
Thanks
BIlla

On Thursday, November 28, 2019 at 7:41:03 PM UTC+5:30, Michael Opdenacker wrote:
Greetings,

I recently made a presentation about embedded Linux on RISC-V, using
QEMU for experiments: https://frama.link/ZvbAu7Qo

As I'm still new to this architecture, don't hesitate to share your
comments and suggestions with me. By the way, the presentation sources
are freely available under the CC-BY-SA license, so don't hesitate to
recycle them if useful ;)

Thanks in advance,

Cheers,

Michael.

--
Michael Opdenacker, CEO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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Jim Wilson

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Dec 19, 2019, 2:42:35 PM12/19/19
to atish patra, Billa Surendra, RISC-V SW Dev
On Thu, Dec 19, 2019 at 12:13 AM atish patra <atis...@gmail.com> wrote:
> On Wed, Dec 18, 2019 at 10:25 PM Billa Surendra <billa.i...@gmail.com> wrote:
>> Excellent presentation for beginners, Who want to make Embedded Linux for RISC-V architecture. I want Help from you for making fedora distro from scratch for RV64IMAFD. Please help me how to start building fedora for RISC-V. Any king of help is appreciable
>
> You don't need to build a fedora distro from scratch. You just need download the prebuilt fedora rootfs image and use it in Qemu as you would have used
> a rootfs generated by buildroot.

Presumably this is a part without the C extension like some (most?)
versions of Shakti. So the prebuilt rootfs isn't going to work.

Building a distro like fedora from scratch is complicated. The
general description of how it was done is here
https://lwn.net/Articles/749443/
That will probably take a few months to set up, and will require a lot
of expertise on how linux works. And then a few more months for the
package rebuilds. Rather than rebuild from scratch, it might be
easier to start with a rv64gc system, and start rebuilding packages
for rv64g. Once you have enough of the core system recompiled, you
can boot on a rv64g system and continue rebuilding packages there.
This is probably only a few months for the package rebuilds. This
still requires some expertise on how linux works, but not as much as
the build from scratch approach.

Jim

Nathan Pemberton

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Dec 19, 2019, 2:47:25 PM12/19/19
to RISC-V SW Dev
Awesome tutorial! I wish I had this earlier :).

You might consider adding a section about the Spike simulator. It's a bit trickier to run (you have to embed the rootfs as an initramfs in the kernel since Spike doesn't have a block device), but it's the most faithful RISC-V implementation (it's the golden model for the ISA, while Qemu has lots of quirks and isn't always totally standards compliant). Spike is also easier to modify if you want to prototype a new device or something. It's mostly more interesting for the hardware development community, but it's a good way to verify if a bug is in your SW or in the HW (especially for things like inline assembly or language/compiler ports). 

I've automated most of these steps in a tool called FireMarshal. It was originally designed to work with FireSim (for hardware development) but it's a pretty easy way to get something similar to these slides up and running. It also helps automate workloads (e.g. for unit/regression testing) and supports Fedora. I'm gonna have to add that networking support, it looks pretty slick.

David Abdurachmanov

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Dec 23, 2019, 7:32:40 AM12/23/19
to Jim Wilson, atish patra, Billa Surendra, RISC-V SW Dev
Hi,

These are exact instructions that I suggest. There is not need to
start from scratch for just disabled RVC because you can mix RV64GC
and RV64G binaries. With enough compute power it should be very quick
to generate a minimal disk image.

david

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> Jim
>
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