riscv-tests for Sv32/Sv39 pattern

[Kimura Masayuki]

Hi all,

I use riscv-tests isa test patterns for checking my RISC-V implementation.

In Sv32 pattern like riscv-tests/isa/rv32ui-v-add, I used spike to check correct behavior but at last test pattern seems to be go infinite loop.

$ spike -l --isa=rv32gc rv32ui-v-add 2> rv32ui-v-add.out32

# spike version f38dcde, riscv-tests 6a1a38d 

...

3 0xffffffff800000b8 (0x07c52f83) x31 0x0000000000000000

core   0: 0xffffffff800000bc (0x02852503) lw      a0, 40(a0)

3 0xffffffff800000bc (0x02852503) x10 0x0000000000000000

core   0: 0xffffffff800000c0 (0x10200073) sret

core   0: exception trap_instruction_access_fault, epc 0x0000000000002ab8

core   0:           badaddr 0x0000000000002ab8

core   0: 0x00000000ffc000c4 (0x14011173) csrrw   sp, sscratch, sp

1 0x00000000ffc000c4 (0x14011173) x 2 0xffffffffffc08368

core   0: 0xffffffffffc000c8 (0x00112223) sw      ra, 4(sp)

1 0xffffffffffc000c8 (0x00112223)

core   0: 0xffffffffffc000cc (0x00312623) sw      gp, 12(sp)

1 0xffffffffffc000cc (0x00312623)

core   0: 0xffffffffffc000d0 (0x00412823) sw      tp, 16(sp)

1 0xffffffffffc000d0 (0x00412823)

core   0: 0xffffffffffc000d4 (0x00512a23) sw      t0, 20(sp)

1 0xffffffffffc000d4 (0x00512a23)

...

By the way, after sret, generating page fault is correct in this pattern?

Thanks.

Masayuki Kimura

[Andrew Waterman]

I ran the same test successfully with a clean installation of
riscv-tools (which points to the same versions of spike and tests).

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[Kimura Masayuki]

Thanks, I checked my implementation and test pattern, and I have a question about riscv-tests/env/vm.c@9e219c9

I understood physical and virtual address are converted by pa2kva, and its implementation is:

#define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE)

But setting sepc for jumping after sret is only:

tf.epc = test_addr - DRAM_BASE;

I think test_addr should also be converted by pa2kva, so

tf.epc = pa2kva(test_addr);

is correct, my understanding is right?

Thanks.

Masayuki Kimura

2017年2月16日(木) 4:57 Andrew Waterman <and...@sifive.com>: