Best,
Alex
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Best,
Alex
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On Thu, Sep 7, 2017 at 7:59 AM, Bruce Hoult <br...@hoult.org> wrote:
> A C.ADDI works for arbitrary frame sizes up to 16 bytes, and a single
> C.ADDI16SP plus a C.ADDI can be used together for arbitrary frame sizes up
> to about 512 bytes.
You might as well just use ADDI at that point (same code size, single
opcode, easier to decode, potentially faster, never slower).
Personally, in my compiler work (Oberon and Forth) I utterly ignore
the 16-byte alignment requirement, and stick with native register
width alignment.
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RV32Q was a legal combination at the time we decided to have 16-byte
stack alignment for RV32. Sometime later, the ISA spec was amended to
make the statement you quoted.
On Thu, Sep 7, 2017 at 11:18 AM, Bruce Hoult <br...@hoult.org> wrote:
> I quote from the RISC-V spec manual, first para, section 12:
>
> 'The 128-bit or quad-precision binary floating-point instruction subset is
> named “Q”, and requires RV64IFD.'
>
> So I ask again: why apply 16 byte alignment to RV32?
>
> On Thu, Sep 7, 2017 at 9:12 PM, Stefan O'Rear <sor...@gmail.com> wrote:
>>
>> On Thu, Sep 7, 2017 at 10:14 AM, Bruce Hoult <br...@hoult.org> wrote:
>> > If you don't have double precision FP then 4 bytes is enough on a 32 bit
>> > system. 8 is enough on a 64 bit system even with FP.
>>
>> 16 was chosen because of the possible presence of the Q extension.
>>
>> -s
>>
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Em 08-09-2017 13:59, Andrew Waterman escreveu:
Good points, David.
A compromise is to keep the ABI stake alignment, and add a stack-alignment flag, so embedded developers can reduce it below the ABI requirement.
The problem with adding a flag is that users might compile code with the flag, which works *for now*... until some dynamic library gets upgraded, and starts using new instructions which require the ABI-specified alignment.
This has recently happened with Fedora: the 32-bit x86 C library was upgraded to a newer version, and this new version used aligned vector instructions to the stack. That broke binary-only programs which were compiled assuming a smaller alignment. The solution was to disable modern vector instructions for the 32-bit x86 C library (which exists mostly for compatibility, modern Fedora is 64-bit).
IMO, the ideal minimum stack alignment for RISC-V should be 2*XLEN, since a future extension might want to implement double-wide LR/SC (or double-wide CAS). For RV32, however, I'd argue that the ideal minimum stack alignment should also be the same as RV64, since RV32G also has 64-bit registers (for floating-point). And as another potential argument, a packed vector with 4 32-bit elements would also be naturally aligned when using a 16-byte alignment. Therefore, it seems to me that 16-byte stack alignment is a sweet spot.
On 9 Sep 2017, at 21:09, Bruce Hoult <br...@hoult.org> wrote:
>
> Note that I'm talking about doing this only on CPUs that *don't* have any instructions requiring large alignment.
The problem with this argument is that very few binaries (outside of firmware and the purely embedded space where the compiler is free to disregard the ABI entirely) ever target a CPU, they target an ISA and they need to interoperate with code that targets a superset of that ISA
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David
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