RISC-V processor Verified FPGA implementable Verilog codes

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Rahul Shandilya

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Jul 5, 2017, 2:11:08 AM7/5/17
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Dear sir,

Please suggest me the RISC-V processor  HDl codes in verilog, that is verified on FPGA by any body. I have found lots of Verilog code on internet, but I am unable to run these code on FPGA. 

Thank You very much for ur suggestion..

--
With Best Regards..

Rahul

Richard Herveille

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Jul 5, 2017, 4:02:34 AM7/5/17
to Rahul Shandilya, isa...@groups.riscv.org
Try the RV12 it's on GitHub; github.com/roalogic. It's written in System Verilog and implemented in FPGA and ASIC. 

Cheer,
Richard 


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Joel Vandergriendt

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Jul 5, 2017, 1:00:10 PM7/5/17
to Richard Herveille, Rahul Shandilya, isa...@groups.riscv.org
May I suggest ORCA? https://github.com/VectorBlox/orca

It is written in VHDL rather than Verilog, but it is written for FPGAs by an FPGA shop. We support xilinx, intel(altera), microsemi and lattice FPGAs.

Joel
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Bruce Hoult

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Jul 5, 2017, 3:28:40 PM7/5/17
to Joel Vandergriendt, Richard Herveille, Rahul Shandilya, isa...@groups.riscv.org
It would be interesting to have an indication of how many LUTs etc are required on different families for common settings.

On Wed, Jul 5, 2017 at 7:59 PM, Joel Vandergriendt <jo...@vectorblox.com> wrote:
May I suggest ORCA? https://github.com/VectorBlox/orca

It is written in VHDL rather than Verilog, but it is written for FPGAs by an FPGA shop. We support xilinx, intel(altera), microsemi and lattice FPGAs.

Joel
On Wed, Jul 5, 2017 at 1:02 AM Richard Herveille <richard.herveille@roalogic.com> wrote:
Try the RV12 it's on GitHub; github.com/roalogic. It's written in System Verilog and implemented in FPGA and ASIC. 

Cheer,
Richard 


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On 5 Jul 2017, at 08:11, Rahul Shandilya <rss....@gmail.com> wrote:

Dear sir,

Please suggest me the RISC-V processor  HDl codes in verilog, that is verified on FPGA by any body. I have found lots of Verilog code on internet, but I am unable to run these code on FPGA. 

Thank You very much for ur suggestion..

--
With Best Regards..

Rahul

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Richard Herveille

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Jul 5, 2017, 4:06:11 PM7/5/17
to Bruce Hoult, Richard Herveille, Joel Vandergriendt, Rahul Shandilya, isa...@groups.riscv.org
Define common settings, what are you looking for?
With/without caches, with/without branch prediction, what extensions, 32/64bit, what supported privilege levels, … ??

Richard




Richard Herveille
Managing Director
Cell +31 (6) 5207 2230




Bruce Hoult

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Jul 5, 2017, 4:18:30 PM7/5/17
to Richard Herveille, Joel Vandergriendt, Rahul Shandilya, isa...@groups.riscv.org
According to information there, there is no support available for 64 bit or branch prediction. I get the impression there is also no support for cache. And possibly not privilege levels either.

So we have an option of with or without hardware multiply and/or divide, how many cycles a maximal shift takes (1, 8, 32). And not a lot else.

The size for a minimal RV32I would certainly be interesting.

On Wed, Jul 5, 2017 at 11:06 PM, Richard Herveille <richard....@roalogic.com> wrote:
Define common settings, what are you looking for?
With/without caches, with/without branch prediction, what extensions, 32/64bit, what supported privilege levels, … ??

Richard



Richard Herveille
Managing Director
Cell +31 (6) 5207 2230




On 05 Jul 2017, at 21:28, Bruce Hoult <br...@hoult.org> wrote:

It would be interesting to have an indication of how many LUTs etc are required on different families for common settings.
On Wed, Jul 5, 2017 at 7:59 PM, Joel Vandergriendt <jo...@vectorblox.com> wrote:
May I suggest ORCA? https://github.com/VectorBlox/orca

It is written in VHDL rather than Verilog, but it is written for FPGAs by an FPGA shop. We support xilinx, intel(altera), microsemi and lattice FPGAs.

Joel
On Wed, Jul 5, 2017 at 1:02 AM Richard Herveille <richard....@roalogic.com> wrote:
Try the RV12 it's on GitHub; github.com/roalogic. It's written in System Verilog and implemented in FPGA and ASIC. 

Cheer,
Richard 


Sent from my iPhone

On 5 Jul 2017, at 08:11, Rahul Shandilya <rss....@gmail.com> wrote:

Dear sir,

Please suggest me the RISC-V processor  HDl codes in verilog, that is verified on FPGA by any body. I have found lots of Verilog code on internet, but I am unable to run these code on FPGA. 

Thank You very much for ur suggestion..

--
With Best Regards..

Rahul


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Guy Lemieux

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Jul 5, 2017, 4:41:17 PM7/5/17
to Bruce Hoult, Richard Herveille, Joel Vandergriendt, Rahul Shandilya, isa...@groups.riscv.org
I've attached an old datasheet based on our old release.

Note the Lattice numbers tend to be for the full system, not just the CPU, because it is not possible to get a hierarchical breakdown of area with the iCEcube tools.

Our new release was just last month, and I still need to update the datasheet.

Guy


On Wed, Jul 5, 2017 at 1:18 PM, Bruce Hoult <br...@hoult.org> wrote:
According to information there, there is no support available for 64 bit or branch prediction. I get the impression there is also no support for cache. And possibly not privilege levels either.

So we have an option of with or without hardware multiply and/or divide, how many cycles a maximal shift takes (1, 8, 32). And not a lot else.

The size for a minimal RV32I would certainly be interesting.

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2016-11-28 ORCA_datasheet.pdf

Fabjan Sukalia

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Jul 5, 2017, 4:42:44 PM7/5/17
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-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256

There is already an incomplete and outdated list of RISC-V cores in the wiki: https://github.com/riscv/riscv-wiki/wiki/RISC-V-Cores-and-SoCs
It would be nice to have public list of cores that are verified by the foundation. This list can also be combined with the list of vendor IDs for open source projects.

Also I think this discussion is better suited for the hw-dev mailing list than here.

- --

Fabjan


On 2017-07-05 22:18, Bruce Hoult wrote:
> According to information there, there is no support available for 64 bit or branch prediction. I get the impression there is also no support for cache. And possibly not privilege levels either. > > So we have an option of with or without hardware multiply and/or divide, how many cycles a maximal shift takes (1, 8, 32). And not a lot else. > > The size for a minimal RV32I would certainly be interesting. > > On Wed, Jul 5, 2017 at 11:06 PM, Richard Herveille <richard....@roalogic.com <mailto:richard....@roalogic.com>> wrote: > > Define common settings, what are you looking for? > With/without caches, with/without branch prediction, what extensions, 32/64bit, what supported privilege levels, … ?? > > Richard > > > > > Richard Herveille > Managing Director > Phone +31 (45) 405 5681 > Cell +31 (6) 5207 2230 > richard....@roalogic.com <mailto:richard....@roalogic.com> > > > > > >> On 05 Jul 2017, at 21:28, Bruce Hoult <br...@hoult.org <mailto:br...@hoult.org>> wrote: >> >> It would be interesting to have an indication of how many LUTs etc are required on different families for common settings. >> >> On Wed, Jul 5, 2017 at 7:59 PM, Joel Vandergriendt <jo...@vectorblox.com <mailto:jo...@vectorblox.com>> wrote: >> >> May I suggest ORCA? https://github.com/VectorBlox/orca <https://github.com/VectorBlox/orca> >> >> It is written in VHDL rather than Verilog, but it is written for FPGAs by an FPGA shop. We support xilinx, intel(altera), microsemi and lattice FPGAs. >> >> Joel >> >> On Wed, Jul 5, 2017 at 1:02 AM Richard Herveille <richard....@roalogic.com <mailto:richard....@roalogic.com>> wrote: >> >> Try the RV12 it's on GitHub; github.com/roalogic <http://github.com/roalogic>. It's written in System Verilog and implemented in FPGA and ASIC. >> >> Cheer, >> Richard >> >> >> Sent from my iPhone >> >> On 5 Jul 2017, at 08:11, Rahul Shandilya <rss....@gmail.com <mailto:rss....@gmail.com>> wrote: >> >>> Dear sir, >>> >>> Please suggest me the RISC-V processor HDl codes in verilog, that is verified on FPGA by any body. I have found lots of Verilog code on internet, but I am unable to run these code on FPGA. >>> >>> Thank You very much for ur suggestion.. >>> >>> -- >>> With Best Regards.. >>> >>> *Rahul* >>> >>> >>> -- >>> You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group. >>> To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+u...@groups.riscv.org <mailto:isa-dev+u...@groups.riscv.org>. >>> To post to this group, send email to isa...@groups.riscv.org <mailto:isa...@groups.riscv.org>. >>> Visit this group at https://groups.google.com/a/groups.riscv.org/group/isa-dev/ <https://groups.google.com/a/groups.riscv.org/group/isa-dev/>. >>> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CADM_pFiPy%3DyHAEjj4Tv%3D4%3DV7JcNJp2kD--%3DAYykRjvy-x4hw1A%40mail.gmail.com <https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CADM_pFiPy%3DyHAEjj4Tv%3D4%3DV7JcNJp2kD--%3DAYykRjvy-x4hw1A%40mail.gmail.com?utm_medium=email&utm_source=footer>. >> >> -- >> You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group. >> To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+u...@groups.riscv.org <mailto:isa-dev+u...@groups.riscv.org>. >> To post to this group, send email to isa...@groups.riscv.org <mailto:isa...@groups.riscv.org>. >> Visit this group at https://groups.google.com/a/groups.riscv.org/group/isa-dev/ <https://groups.google.com/a/groups.riscv.org/group/isa-dev/>. >> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/E55026F6-8455-4019-BA89-76BF8B7B4F52%40roalogic.com <https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/E55026F6-8455-4019-BA89-76BF8B7B4F52%40roalogic.com?utm_medium=email&utm_source=footer>. >> >> >> -- >> You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group. >> To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+u...@groups.riscv.org <mailto:isa-dev+u...@groups.riscv.org>. >> To post to this group, send email to isa...@groups.riscv.org <mailto:isa...@groups.riscv.org>. >> Visit this group at https://groups.google.com/a/groups.riscv.org/group/isa-dev/ <https://groups.google.com/a/groups.riscv.org/group/isa-dev/>. >> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CABq8-isCrcGEArUqPkbtGTKK05TWG7D3AG8_zY5O69u%2B9-Gy3A%40mail.gmail.com <https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CABq8-isCrcGEArUqPkbtGTKK05TWG7D3AG8_zY5O69u%2B9-Gy3A%40mail.gmail.com?utm_medium=email&utm_source=footer>. >> >> > > -- > You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group. > To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+u...@groups.riscv.org <mailto:isa-dev+u...@groups.riscv.org>. > To post to this group, send email to isa...@groups.riscv.org <mailto:isa...@groups.riscv.org>. > Visit this group at https://groups.google.com/a/groups.riscv.org/group/isa-dev/ <https://groups.google.com/a/groups.riscv.org/group/isa-dev/>. > To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/2182A6CB-DE2D-4F3B-8EF7-6D342F96F388%40roalogic.com <https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/2182A6CB-DE2D-4F3B-8EF7-6D342F96F388%40roalogic.com?utm_medium=email&utm_source=footer>. > > > -- > You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group. > To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+u...@groups.riscv.org <mailto:isa-dev+u...@groups.riscv.org>. > To post to this group, send email to isa...@groups.riscv.org <mailto:isa...@groups.riscv.org>. > Visit this group at https://groups.google.com/a/groups.riscv.org/group/isa-dev/. > To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CAMU%2BEkyEDXC_y5kRcpNiuD2YaT-LQ52hw%2BDwpVtZ1RZgTJsiVQ%40mail.gmail.com <https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/CAMU%2BEkyEDXC_y5kRcpNiuD2YaT-LQ52hw%2BDwpVtZ1RZgTJsiVQ%40mail.gmail.com?utm_medium=email&utm_source=footer>.
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Richard Herveille

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Jul 5, 2017, 6:44:04 PM7/5/17
to Fabjan Sukalia, isa...@groups.riscv.org
Ah, well I was referring to our implementation; the RV12. 

Richard 


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