Capturing RISC V instructions

[Amr Zaky]

Hi

I am not sure if this is the suitable forum for this question, but please guide me if there is a more appropriate forum to ask it.

I want to get RISC V instruction traces to feed an educational microarchitectural trace. We're talking here about the Hennessy and Patterson (book 2) kind of microarchitecture: advanced cache techniques, dynamic scheduling, speculation, etc.

Towards that end, I was able to install the RISC V toolchain on a  VMWare Linux client on my PC. I was "almost" able to get the Spike  instruction set simulator installed correctly. 

Before I put more effort into fixing the Spike installation, I want to be reassured that there is a path of using it to acquire an instruction trace. One-at-a-time is fine, instruction file is also fine, speed is not an issue (the assignments will be mostly simple loops like DAXPY). 

If there is a way to get the instructions executed from Spike, please explain it to me in some detail, considering I am mostly an Architect/Professor rather than a very experienced SW guru.

In the past, people pointed to FPGAs and commercial tools, unfortunately, our school circumstances do not make use of this possible. 

Thanks

--Amr Zaky

[Olof Kindgren]

Hi Amr,

I haven't used Spike and can't comment on that, but from your description I would recommend looking into RVFPGA. (https://university.imgtec.com/teaching-download/) It is a widely used free computer architecture course based on RISC-V. It comes with a bunch of labs which can be run on a real FPGA board or completely in simulation using a virtual FPGA board. It also comes with a pipeline viewer to graphically follow instructions as they pass through the CPU and other things.

Best,

Olof

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[Ved Shanbhogue]

Amr Hi -

Please see if "  -l                    Generate a log of execution" option is what you were looking for.

Example log:

core   0: 0x80000120 (0xf8000eb7) lui     t4, 0xf8000
core   0: 0x80000124 (0xfffe8e93) addi    t4, t4, -1
core   0: 0x80000128 (0x01d0a023) sw      t4, 0(ra)
core   0: 0x8000012c (0x80000eb7) lui     t4, 0x80000
core   0: 0x80000130 (0x00008f93) mv      t6, ra
core   0: 0x80000134 (0x01dfaf2f) amoadd.w t5, t4, (t6)
core   0: 0x80000138 (0x01e0a223) sw      t5, 4(ra)
core   0: 0x8000013c (0xf8000fb7) lui     t6, 0xf8000

regards

ved

[Dmitry Belimov]

Hi,

I use Spike to generate trace log to compare how to execute a program
with my core in Icarus Verilog.

my example:

spike --isa=RV32I_zicsr --priv=m
-m0x20000000:0x8000,0x20100000:0x1000,0x8000000:0x100000 -d
--debug-cmd=spike.cmd --log-commits -l --log=progname_spike.log
progname.elf

where:

-m0x20000000:0x8000,0x20100000:0x1000,0x8000000:0x100000 determine
memory region:

- 0x20000000 size 0x8000 - program RAM
- 0x20100000 size 0x1000 - pheripherial mapped RAM
- 0x80000000 size 0x100000 - Flash

--log-commits set to generate logfile with information about data. What
is data read/write to/from reg/memory.

spike.cmd is a file with simple command flow. In may case it is:

until pc 0 0x80000090 // execute a program until Program counter not
0x80000090
r 1 // execute a program 1 step
quit // stop emulation and exit

Best regards,

Amr Zaky писал 29-08-2024 03:01:

> Hi
> I am not sure if this is the suitable forum for this question, but
> please guide me if there is a more appropriate forum to ask it.
>
> I want to get RISC V instruction traces to feed an educational

> microarchitectural trace. Were talking here about the Hennessy and

> Patterson (book 2) kind of microarchitecture: advanced cache
> techniques, dynamic scheduling, speculation, etc.
>
> Towards that end, I was able to install the RISC V toolchain on a 
> VMWare Linux client on my PC. I was "almost" able to get the Spike 
> instruction set simulator installed correctly. 
>
> Before I put more effort into fixing the Spike installation, I want
> to
> be reassured that there is a path of using it to acquire an
> instruction trace. One-at-a-time is fine, instruction file is also
> fine, speed is not an issue (the assignments will be mostly simple
> loops like DAXPY). 
>
> If there is a way to get the instructions executed from Spike, please
> explain it to me in some detail, considering I am mostly an
> Architect/Professor rather than a very experienced SW guru.
>
> In the past, people pointed to FPGAs and commercial tools,
> unfortunately, our school circumstances do not make use of this
> possible. 
>
> Thanks
> --Amr Zaky
>

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[Tommy Murphy]

Others have provided useful info on how to use Spike to log instruction execution but I just wanted to comment on a few other things...

> I want to get RISC V instruction traces to feed an educational microarchitectural trace. We're talking here about the Hennessy and Patterson (book 2) kind of microarchitecture: advanced cache techniques, dynamic scheduling, speculation, etc.

If you want to model/simulate/analyse specific microarchitectural features then I'm not sure that Spike is necessarily going to do that for you given that it's a RISC-V ISA simulator and not a simulator for specific microarchitectural features?

> Towards that end, I was able to install the RISC V toolchain on a  VMWare Linux client on my PC. I was "almost" able to get the Spike  instruction set simulator installed correctly. 

> Before I put more effort into fixing the Spike installation

I'm not sure what you're referring to here but, in my experience, building and installing the RISC-V bare-metal/Newlib toolchain and Spike on any recent Linux distro as follows works simply and reliably:

# Install prerequisite packages

# https://github.com/riscv-collab/riscv-gnu-toolchain?tab=readme-ov-file#prerequisites

# https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1251

git clone https://github.com/riscv-collab/riscv-gnu-toolchain

cd riscv-gnu-toolchain

# Add --enable-multilib for the default set of multilibs

# Or use --with-multilib-generator for a custom set of bare-metal toolchain multilibs

# https://github.com/riscv-collab/riscv-gnu-toolchain?tab=readme-ov-file#build-with-customized-multi-lib-configure

./configure --prefix=`pwd`/installed-tools --with-sim=spike

make 

make build-sim

# Toolchain binaries are now in `pwd`/installed-tools/bin

However, I have always struggled to use Spike to run simple bare-metal programs and there doesn't seem to be one single source of clear explanatory information on how to do this so it's necessary to search/read more widely and be guided by existing examples. I've seen it suggested that a good place to start may be the RISC-V tests to see how they utilise Spike:

https://github.com/riscv-software-src/riscv-tests

> please explain it to me in some detail

Others have posted some useful info but the best way is probably to run Spike with the -l option yourself and see what you get.

https://github.com/riscv-software-src/riscv-isa-sim/blob/272c149f37100780dc97df4661561f17ea5dc1d5/spike_main/spike.cc#L36 

[Guy Lemieux]

do you want students to write their own microarchitecture simulator, or to optimize code for a specific microarchitecture?

look into valgrind/cachegrind, which would

be useful for the latter. the risc-v port is incomplete, and I think you need a HiFive Unmatched board ($300), but maybe there is a way to get it to run under Spike as well.

g

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[Rishiyur Nikhil]

Or, instead of Spike, you could build and run the official formal
specification for the RISC-V ISA:

    https://github.com/riscv/sail-riscv

This also produces an instruction-by-instruction trace.

Nikhil

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