mv pseudo-instruction

[Michael Clark]

I have been reading objdump output from gcc and noticed that the compiler is using ‘add’ instead of ‘addi’ for the ‘mv’ pseudo-instruction and that ‘mv’ as defined in the Base ISA specification pseudo-instructions appears to only be used to ‘zero’ registers. e.g. addi with 0 immediate has zero as the source register when translating to the ‘mv’ pseudo using the specification pattern.

There are a small number of cases (the exception) where ‘mv’ is actually a ‘mv’ and it seems to always be moving sp into s0. The bulk of the moves are using add with zero, not addi with 0.

Interestingly I don’t see add rd, zero, zero being used to clear registers, rather the zero + 0 immediate is used.

Table 20.2: RISC-V pseudoinstructions.

This is what the table currently lists:

mv rd, rs       addi rd, rs, 0 Copy register

This would better represent the output I am seeing from gcc and would be semantically compatible:

mv rd, zero     addi rd, zero, 0        Zero register

mv rd, rs       add rd, zero, rs        Copy register

Alternatively a zero psuedo could be added, which is an additive change that is semantically backwards compatible:

zero rd         addi rd, zero, 0        Zero register

mv rd, rs       add rd, zero, rs        Copy register

I noticed because I am working on lifting 1:1 psuedo-instructions and coalescing 2:1 macro-op pseudo-instructions from disassembly into pseudo opcodes for translation and a zero pseudo would be useful as a distinct pseudo op as it might translate to `xor r10, r10` on an architectures that doesn’t have a zero register.

[Rogier Brussee]

This is probably because the Compact extension lists in the integer register register instructions:

C.MV expands in add rd zero rs2  

moreover rs2 != x0 so to zero a register you have to use li rd 0 which expands to addi rd zero 0

So I agree that it would be wise to change the definition of the pseudo instructions so that they better reflect (potential) C capable hardware.

Rogier

Op woensdag 1 maart 2017 22:55:26 UTC+1 schreef michaeljclark:

[Andrew Waterman]

gcc should be using mv to copy registers. Could you submit a bug
report & test case to the riscv-gcc github issue tracker if it fails
to do so?

I don't think we need a new pseudo-op to zero a register, as li rd, 0
gets the point across fine.

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[Michael Clark]

> On 2 Mar 2017, at 11:34 AM, Andrew Waterman <and...@sifive.com> wrote:
>
> gcc should be using mv to copy registers. Could you submit a bug
> report & test case to the riscv-gcc github issue tracker if it fails
> to do so?

OK. It is just eyeballing asm. I’m not sure what C program creates mv.

Definitely seeing “add rd, zero, rs2” pattern for mv versus “addi rd, rs1, 0”.

$ ls -l `which riscv64-unknown-elf-gcc`
-rwxr-xr-x 2 mclark mclark 5181232 Feb 15 19:44 /opt/riscv/toolchain/bin/riscv64-unknown-elf-gcc

$ rv-bin dump -a linux-4.6.2/vmlinux | grep "add " | grep zero | head
800000d0: 892a add s2, zero, a0
800000d2: 8b2e add s6, zero, a1
800000f4: 854a add a0, zero, s2
80000104: 854a add a0, zero, s2
8000010e: 855a add a0, zero, s6
80000114: 85ca add a1, zero, s2
800001b2: 892a add s2, zero, a0
800001b6: 85aa add a1, zero, a0
800001c2: 85ce add a1, zero, s3
800001c4: 8556 add a0, zero, s5

> I don't think we need a new pseudo-op to zero a register, as li rd, 0
> gets the point across fine.

li rd, 0 is okay.

The point was more that the emitted opcode for the 0 case could be different so it might be useful in a translation layer. e.g. a pseudo mapping vs a special case based on the immediate value. np.

[Michael Clark]

https://github.com/riscv/riscv-gcc/issues/49

[Michael Clark]

I think it might be Binutils/gas

$ grep mv build/riscv64-unknown-elf/sample-asm/test-*rv64.s
build/riscv64-unknown-elf/sample-asm/test-loop-2-rv64.s: mv a1,a5
build/riscv64-unknown-elf/sample-asm/test-loop-3-rv64.s: mv a1,a5
build/riscv64-unknown-elf/sample-asm/test-module-1a-rv64.s: mv a0,a1
build/riscv64-unknown-elf/sample-asm/test-module-1a-rv64.s: mv a1,a0
build/riscv64-unknown-elf/sample-asm/test-thread-1-rv64.s: mv s0,a0

On 2 Mar 2017, at 11:49 AM, Michael Clark <michae...@mac.com> wrote:

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[Michael Clark]

Andrew figured it out. I didn’t realise I was looking at RVC output as this is enabled by default now.

It seems RVC uses x0 for moves whereas RVI uses 0 immediate for moves. Minor inconsistency.

I have no idea as to whether this makes any difference in terms of energy as there are two options on RVI.

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[Michael Clark]

On 2 Mar 2017, at 12:33 PM, Michael Clark <michae...@mac.com> wrote:

Andrew figured it out. I didn’t realise I was looking at RVC output as this is enabled by default now.

It seems RVC uses x0 for moves whereas RVI uses 0 immediate for moves. Minor inconsistency.

I have no idea as to whether this makes any difference in terms of energy as there are two options on RVI.

On 2 Mar 2017, at 11:30 AM, Rogier Brussee <rogier....@gmail.com> wrote:

This is probably because the Compact extension lists in the integer register register instructions:

C.MV expands in add rd zero rs2  

moreover rs2 != x0 so to zero a register you have to use li rd 0 which expands to addi rd zero 0

So I agree that it would be wise to change the definition of the pseudo instructions so that they better reflect (potential) C capable hardware.

Yes. It seems if the RVI mv pseudo was “add rd, zero, rs2” vs “addi rd, rs1, 0” then the decompressed forms for RVI and RVC would be equivalent. Minor nit.

RVI is indeed using addi 0 and RVC is indeed using add zero. However the compiler is compressing them correctly either way.

A disassembler technically needs to detect 3 forms of RVI move (addi, and add with zero in either rs1 or rs2) plus the RVC form.