[Question] TileLink communication and interface

[adaptiveprocessor]

Hi All,

I am not familiar with NoC, and have a level of introduction knowledge.

I have read specification note of this;

https://static.dev.sifive.com/docs/tilelink/tilelink-spec-1.7-draft.pdf

Then rises several questions;

1) Is the TileLink, standard NoC router arhitecture?

There is no description about flit buffers, arbitor, xbar, but supports a burst transmission.

It is just like a port definision (they call as Master/Slave Agent) with a memory map.

2) There is no explanation about interfacing between the TileLink and Processor/Local Memory

Can the agent be the processor core (or its cache memory)?

3) There is no explanation about how memory map affects to the communication.

How connected between TileLink and processor/memory is unknown, I need an example.

4) I want NoC router which supports a load from/store to a local memory in a tile, is this supported?

If not supported, is alternative NoC available for this style?

Best Regards,

S.Takano

[adaptiveprocessor]

In addition,

5) There is no explanation of example with a software pogram.

MPI, OpenMP or somthing API su@ported or manually coding is necessary (although depending on tile architecture but I want to talk about the rocket microprocessor as an example)

This information is very helpful to understand the TileLink architecture based tile.

Best,

S.Takano

[Stefan O'Rear]

On Thu, Jan 11, 2018 at 12:16 AM, adaptiveprocessor
<adaptive...@gmail.com> wrote:
> On Thursday, January 11, 2018 at 5:10:38 PM UTC+9, adaptiveprocessor wrote:
>>
>> Hi All,
>>
>> I am not familiar with NoC, and have a level of introduction knowledge.
>> I have read specification note of this;
>>
>> https://static.dev.sifive.com/docs/tilelink/tilelink-spec-1.7-draft.pdf
>>
>> Then rises several questions;
>>
>> 1) Is the TileLink, standard NoC router arhitecture?
>> There is no description about flit buffers, arbitor, xbar, but supports a
>> burst transmission.
>> It is just like a port definision (they call as Master/Slave Agent) with a
>> memory map.

TileLink is designed for a tree topology, not a NoC topology, and
unless I misunderstand the question it has no concept of a flit
buffer. TileLink is a port definition but arbiters, crossbars, and
other miscellany can be found in the rocket-chip repository under
https://github.com/freechipsproject/rocket-chip/tree/master/src/main/scala/tilelink
.

>> 2) There is no explanation about interfacing between the TileLink and
>> Processor/Local Memory
>> Can the agent be the processor core (or its cache memory)?

TileLink is used for communication between caches and between caches
and peripherals; a core or its L1 cache can indeed be a TileLink
agent. Rocket implements TileLink at the L1 level; communication
between the Rocket core and Rocket L1 cache uses a different protocol,
which is called "Hella" and appears to be entirely undocumented.

>> 3) There is no explanation about how memory map affects to the
>> communication.
>> How connected between TileLink and processor/memory is unknown, I need an
>> example.

I don't understand the question.

>> 4) I want NoC router which supports a load from/store to a local memory in
>> a tile, is this supported?
>> If not supported, is alternative NoC available for this style?

TileLink's signal level requires that networks contain no cycles, so
cannot be used for a NoC. You could define a NoC protocol to carry
TileLink messages, but AFAIK there is no existing example.

> In addition,
>
> 5) There is no explanation of example with a software pogram.
> MPI, OpenMP or somthing API su@ported or manually coding is necessary
> (although depending on tile architecture but I want to talk about the rocket
> microprocessor as an example)

I don't understand what OpenMP has to do with a port specification.

> This information is very helpful to understand the TileLink architecture
> based tile.

-s

[kr...@berkeley.edu]

TileLink is agnostic to the physical transport, so can be carried over
various meshes / k-ary n-cubes, for example. A mesh can be viewed as
a big distributed crossbar connecting TileLink masters to TileLink
slaves.

Krste

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[Alex Solomatnikov]

TileLink is a higher level protocol than what you call NoC (flits, buffers, etc.). It is used for cache coherence implementation and simpler things like access to uncached memories and devices.

It can be layered on top of different NoCs/NoC protocols, however, some constraints are probably required, e.g. messages cannot be nacked, dropped, re-ordered, etc.

Alex

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[adaptiveprocessor]

Thank you all,

I understand the TileLink is definition of port and its protocol.

So we can assemble NoC Router with the TileLink.

And so I should ask of you about is there specification document of a mesh router architecture used in rocket?

I had mixed and confused, so I had question about a programming model and such higher level things.

But I still does not understand that how memory address works for the porting (just in my curiosity), indeed I must look into Rocket code :)

Best Regards,

S.Takano

On Thursday, January 11, 2018 at 5:10:38 PM UTC+9, adaptiveprocessor wrote:

[kr...@berkeley.edu]

Rocket Chip repo doesn't have a mesh router.

Krste

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