Rocket 32bit Benchmark test with TinyConfig option?

[Matthew Kim]

Hi Community,

Can anyone help me to test Rocket Benchmarks with the TinyConfig option?

The default configuration was "empty-bmark-tests = \" from the "TestHarness.TinyConfig.d" file.

"run-asm-tests" was OK but not "run-bmark-tests"

Can I get some tips for adding the bmarks test? I have simply tried to add the dhryston.risc to the "empty-bmark-tests = \" but it didn't work properly.

Thanks,

Matthew

[Andrew Waterman]

By default those benchmarks expect to run on an RV32IMAFD or RV64IMAFD
system, but TinyConfig is RV32IM. If you build an RV32IM toolchain
and lightly modify the benchmarks Makefile, you should be able to
build a binary that will work.

> --
> You received this message because you are subscribed to the Google Groups
> "RISC-V HW Dev" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to hw-dev+un...@groups.riscv.org.
> To post to this group, send email to hw-...@groups.riscv.org.
> Visit this group at
> https://groups.google.com/a/groups.riscv.org/group/hw-dev/.
> To view this discussion on the web visit
> https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/8f1c9b2d-1baa-426f-b35f-1383622b0ce7%40groups.riscv.org.

[nearers]

Thanks Andrew,

Sorry, I couldn't clearly understand your response. It looks a bit missed the point of my question.

* bmark-tests generation

I have simply tried change this line and it generates bmark-test for the TinyConfig.

https://github.com/ucb-bar/rocket-chip/blob/master/src/main/scala/coreplex/Configs.scala#L96

Could you please explain me the reason of this line?

TestGeneration.addSuite(if (site(UseVM)) benchmarks else emptyBmarks)

* RV32IMAFD - What is the CONFIG to generate this Rocket Option?

The "UseVM option" was false in the basic RV32 option. Do I need to make my own UserConfig to use that RV32IMAFD option?

class WithRV32 extends Config(

  (pname,site,here) => pname match {

    case XLen => 32

    case UseVM => false

    case UseUser => false

    case UseAtomics => false

    case FPUKey => None

    case RegressionTestNames => LinkedHashSet(

      "rv32mi-p-ma_addr",

      "rv32mi-p-csr",

      "rv32ui-p-sh",

      "rv32ui-p-lh",

      "rv32mi-p-sbreak",

      "rv32ui-p-sll")

    case _ => throw new CDEMatchError

  }

)

Thanks and Regards,

Matthew

On 27 August 2016 at 05:36, Andrew Waterman <and...@sifive.com> wrote:

By default those benchmarks expect to run on an RV32IMAFD or RV64IMAFD
system, but TinyConfig is RV32IM.  If you build an RV32IM toolchain
and lightly modify the benchmarks Makefile, you should be able to
build a binary that will work.

On Thu, Aug 18, 2016 at 4:48 AM, Matthew Kim <nea...@gmail.com> wrote:
> Hi Community,
>
> Can anyone help me to test Rocket Benchmarks with the TinyConfig option?
> The default configuration was "empty-bmark-tests = \" from the
> "TestHarness.TinyConfig.d" file.
>
> "run-asm-tests" was OK but not "run-bmark-tests"
>
> Can I get some tips for adding the bmarks test? I have simply tried to add
> the dhryston.risc to the "empty-bmark-tests = \" but it didn't work
> properly.
>
> Thanks,
> Matthew
>
> --
> You received this message because you are subscribed to the Google Groups
> "RISC-V HW Dev" group.
> To unsubscribe from this group and stop receiving emails from it, send an

> email to hw-dev+unsubscribe@groups.riscv.org.

[Andrew Waterman]

That looks like a mistake (or it's covering up some other sin :-)).
I'll make it so those benchmarks run even when UseVM=false.

>> > email to hw-dev+un...@groups.riscv.org.

>> > To post to this group, send email to hw-...@groups.riscv.org.
>> > Visit this group at
>> > https://groups.google.com/a/groups.riscv.org/group/hw-dev/.
>> > To view this discussion on the web visit
>> >
>> > https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/8f1c9b2d-1baa-426f-b35f-1383622b0ce7%40groups.riscv.org.
>
>

> --
> You received this message because you are subscribed to the Google Groups
> "RISC-V HW Dev" group.
> To unsubscribe from this group and stop receiving emails from it, send an

> email to hw-dev+un...@groups.riscv.org.

> To post to this group, send email to hw-...@groups.riscv.org.
> Visit this group at
> https://groups.google.com/a/groups.riscv.org/group/hw-dev/.
> To view this discussion on the web visit

> https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/CAC%2B%2Bh9E0nKb%2BkQfdyys2%3Dzy6%3DiU6XQ%2Bi6CQNHhsmYR7H9HikRA%40mail.gmail.com.

[Nhon]

Mathew,

I tried modifying the line as you suggested below from Xlen=64 to Xlen=32. I still couldn't generate the bmark-tests for the TinyConfig. Was that the right change?

Specifically, after I made the change, I tried to do make -j4 CONFIG=TinyConfig run-bmark-tests and it was able to generate a few tests but timed out at towers.riscv and qsort.riscv, among others.

Nhon

> email to hw-dev+un...@groups.riscv.org.

[nearers]

Hi Nhon,

I am still waiting for the update from Andrew. I have no answer yet.

Could you please let me know if you find any other solution?

Regards,

Matthew

To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+unsubscribe@groups.riscv.org.

To post to this group, send email to hw-...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/hw-dev/.

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/624a6315-327e-4ca7-81f4-99d9b4dc9cd9%40groups.riscv.org.

[재민김]

Basically, if you are stuck at the same situation as I am, then the reason why it times out is because the front part of the generated benchmark binary checks misa register and only continue on the proper execurion path if misa register states that the machine is 64bit. I am trying tk figure out what puts in such code into the beginning part of benchmark, and looking at linker files and etc. Yet I have not found where it comes from, but I hopefully it will be resolved within a short time.
In addition, I found some of the benchmarks are used to verify the single/double precision floating points so those benchmark are, in my opinion, meant to be not executable on TinyConfig.

Note that I am working with a customized configuration which is sligthly modified based on TinyConfig.

2016. 9. 29. 오후 1:31에 "nearers" <nea...@gmail.com>님이 작성:

To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+un...@groups.riscv.org.

To post to this group, send email to hw-...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/hw-dev/.

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/624a6315-327e-4ca7-81f4-99d9b4dc9cd9%40groups.riscv.org.

--
You received this message because you are subscribed to the Google Groups "RISC-V HW Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+unsubscribe@groups.riscv.org.
To post to this group, send email to hw-...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/hw-dev/.

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/CAC%2B%2Bh9FDRondE8POiZVk2f2pCw1Fyc33gPi65V0hFiYR048_vg%40mail.gmail.com.

[Christopher Celio]

Basically, if you are stuck at the same situation as I am, then the reason why it times out is because the front part of the generated benchmark binary checks misa register and only continue on the proper execurion path if misa register states that the machine is 64bit. I am trying tk figure out what puts in such code into the beginning part of benchmark, and looking at linker files and etc.

The riscv-tests/benchmarks are generated with the help of riscv-tests-env (https://github.com/riscv/riscv-test-env), perhaps this is what you're looking for?

https://github.com/riscv/riscv-test-env/blob/master/p/riscv_test.h#L56

-Chris

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/CA%2B1fW8C2C3WetGkt%2BacOo-EFMqB7hLbzjfNt3Y75Zc4%3Dif-7dg%40mail.gmail.com.

[Nhon Quach]

Mathew,

Definitely. I have the same suspicion as Joisty and have been trying to figure out who put the code there in the first place. Looks like some detective work is needed. I hope that there is some documentation along this line since many (too many?) things seem to happen automagically. Parsing Makefiles is not fun. But I must say that the amount of documentation on riscv and the various implemented cores is decent.

Nhon

To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+un...@groups.riscv.org.

To post to this group, send email to hw-...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/hw-dev/.

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/624a6315-327e-4ca7-81f4-99d9b4dc9cd9%40groups.riscv.org.

--

Main: +1 408 888 7248
================================================================
This electronic message transmission contains information from Abee Semi, Inc. which may be confidential or privileged. The information is intended to be for the use of the individual or entity named above. If you are not the intended recipient, be aware that any disclosure, copying, distribution or use of the contents of this information is prohibited. If you have received this electronic transmission in error, please notify us by telephone (408.888.7248) or by electronic mail (nhon....@abeesemi.net) immediately.
================================================================

[Nhon Quach]

Matthew,

Another thing. I am new to this, still trying figure out where the tool picks up the file TinyConfig in "make verilog CONFIG=TinyConfig". Do you know?

Thanks,

Nhon 

[Megan Wachs]

TinyConfig is not a file, it is the name of a class. See rocket-chip/src/main/scala/rocketchip/Configs.scala. 

To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+unsubscribe@groups.riscv.org.

To post to this group, send email to hw-...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/hw-dev/.

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/CACyb0oEgVjkJcEbdOxMiWfdV0c3oyPTKnjhthKq_3EYZ5GjdMg%40mail.gmail.com.

--

Megan A. Wachs

Engineer | SiFive, Inc 

300 Brannan St, Suite 403 

San Francisco, CA  94107 

me...@sifive.com