RSD: a new RISC-V out-of-order superscalar processor

718 views
Skip to first unread message

Susumu Mashimo

unread,
Dec 25, 2019, 2:50:39 AM12/25/19
to RISC-V HW Dev
Hi, I would like to share our new RISC-V out-of-order superscalar processor called RSD.

The key features of RSD are:
  • Written in SystemVerilog
  • Run on a Xilinx Zynq FPGA board
  • Can be simulated with Mentor Modelsim/QuestaSim, Verilator, and Vivado
  • Support RV32IM and Zephyr applications
  • 2-fetch front-end and 5-issue back-end pipelines
  • Up to 64 instructions are in-flight
    • These parameters can be configurable
  • A high-speed speculative instruction scheduler with a replay mechanism
  • Speculative OoO load/store execution and dynamic memory disambiguation
  • Non-blocking L1 data cache
  • Support AXI4 bus
  • Support the Konata pipeline visualizer (https://github.com/shioyadan/Konata)

We presented RSD in the FPT2019 international conference this year.
You can find the pre-print version of our paper here (http://sv.rsg.ci.i.u-tokyo.ac.jp/pdfs/Mashimo-FPT'19.pdf).

Ray Van De Walker

unread,
Dec 28, 2019, 1:54:03 PM12/28/19
to RISC-V HW Dev

Congratulations!

 

From: Susumu Mashimo <mashim...@gmail.com>
to: [hw-dev] RSD: a new RISC-V out-of-order superscalar processor

 

Hi, I would like to share our new RISC-V out-of-order superscalar processor called RSD.

Akira Tsukamoto

unread,
Dec 31, 2019, 4:32:35 AM12/31/19
to Ray Van De Walker, mashim...@gmail.com, RISC-V HW Dev
Nice!

It might be good to request PR here.
https://github.com/riscv/riscv-cores-list

Then it should be automatically reflected to the RISC-V Foundation
page bellow with your great out of order soft cpu.
https://riscv.org/risc-v-cores/

-Akira
> --
> You received this message because you are subscribed to the Google Groups "RISC-V HW Dev" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to hw-dev+un...@groups.riscv.org.
> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/hw-dev/BYAPR20MB26163C4A53D3FD8193467329F0250%40BYAPR20MB2616.namprd20.prod.outlook.com.

Susumu Mashimo

unread,
Jan 1, 2020, 10:59:52 AM1/1/20
to RISC-V HW Dev, mashim...@gmail.com
I opened a PR in the repo you mentioned.
Thank you for your advice.

Susumu Mashimo

unread,
Feb 13, 2020, 11:22:54 PM2/13/20
to RISC-V HW Dev
We updated RSD today!
The main changes are:
Currently Synopsys Synplify is required to boot RSD on FPGA, but we plan to make it depend only on Vivado.


2019年12月25日水曜日 16時50分39秒 UTC+9 Susumu Mashimo:

Susumu Mashimo

unread,
May 6, 2020, 11:27:11 PM5/6/20
to RISC-V HW Dev
We updated RSD today!
We eliminated the dependency of RSD on Synopsys Synplify.
So now you can try RSD on an FPGA board using only Vivado (free)!

Note that Synplify+Vivado provided better operating frequency compared to Vivado only in our evaluation.
Therefore we still remain the option of using Synplify for users who have the license.
See the wiki page for the detail.

In addition, we added the support of post-synthesis simulation for FPGA.
This simulation is helpful for debugging when RSD runs correctly on the functional simulation but an FPGA.

mashim...@gmail.com

unread,
Dec 9, 2020, 5:17:22 AM12/9/20
to RISC-V HW Dev, mashim...@gmail.com
Hi, this is just an FYI but we recently added several features below to RSD.

These features are useful for users who use RSD in a SoC, as RSD can access memory-mapped IO, receive external interrupt, etc.

Regards,
Susumu

2020年5月7日木曜日 12:27:11 UTC+9 mashim...@gmail.com:
Reply all
Reply to author
Forward
0 new messages