Support for SWD DTM : any legal issue ?
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Pierre G.
May 12, 2019, 4:59:34 AM5/12/19
to RISC-V Debug Group
Hello,
Since SWD protocol is an ARM proprietary debug protocol (at least that is my understanding).
Can we design a Riscv device - that does not contain any coresight IP - where DTM relies on SWD without any legal infringement with ARM ?
Thx in advance for your answers.
SEGGER - Alex Gruener
May 13, 2019, 2:45:23 AM5/13/19
to Pierre G., RISC-V Debug Group
Hi,
most vendors went with 2-wire cJTAG (IEEE 1149.7) so far when having either RV only designs or RV + ARM ones.
They usually have the RV behind a DAP and an APB-AP (similar to a Cortex-A based device).
The ARM core (if in the same device) will be behind the same DAP and either another APB-AP or just have its debug registers in a different address space of the APB-AP.
SWD should be possible when having also an ARM core in the same chip.
If it is possible for designs with RV only is something that ARM can answer better...
I am not sure regarding their licensing schemes.
As most went for cJTAG, it sounds a bit like that either the licensing scheme does not match or nobody really knows and they wanted to be on the safe side :)
Alex Gruener
CTO
T +49-2173-99312-0
www.segger.com
most vendors went with 2-wire cJTAG (IEEE 1149.7) so far when having either RV only designs or RV + ARM ones.
They usually have the RV behind a DAP and an APB-AP (similar to a Cortex-A based device).
The ARM core (if in the same device) will be behind the same DAP and either another APB-AP or just have its debug registers in a different address space of the APB-AP.
SWD should be possible when having also an ARM core in the same chip.
If it is possible for designs with RV only is something that ARM can answer better...
I am not sure regarding their licensing schemes.
As most went for cJTAG, it sounds a bit like that either the licensing scheme does not match or nobody really knows and they wanted to be on the safe side :)
Alex Gruener
CTO
T +49-2173-99312-0
www.segger.com
SEGGER Microcontroller GmbH * Ecolab-Allee 5 * 40789
Monheim am Rhein * Germany * Tel.
+49-2173-99312-0 * Fax. +49-2173-99312-28
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Director: Ivo Geilenbruegge
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Jim Wang
May 19, 2019, 11:20:19 PM5/19/19
to SEGGER - Alex Gruener, Pierre G., RISC-V Debug Group
Hi Alex,
Thank you.
Do you know the status of ATE support on cJTAG? I’m wondering whether we can still combine testing port and debug port if we use cJTAG. If so, it can be really helpful to save some pins.
But the following question would be the speed difference if using cJTAG for testing. “Time is money, my friend.”
Thanks.
Regards,
Jim Wang
Hi,
most vendors went with 2-wire cJTAG (IEEE 1149.7) so far when having either RV only designs or RV + ARM ones.
They usually have the RV behind a DAP and an APB-AP (similar to a Cortex-A based device).
The ARM core (if in the same device) will be behind the same DAP and either another APB-AP or just have its debug registers in a different address space of the APB-AP.
SWD should be possible when having also an ARM core in the same chip.
If it is possible for designs with RV only is something that ARM can answer better...
I am not sure regarding their licensing schemes.
As most went for cJTAG, it sounds a bit like that either the licensing scheme does not match or nobody really knows and they wanted to be on the safe side :)
SEGGER Microcontroller GmbH * Ecolab-Allee 5 * 40789 Monheim am Rhein * Germany * Tel. +49-2173-99312-0 * Fax. +49-2173-99312-28
Amtsgericht Düsseldorf, HRB-Nr.: 57453 * Managing Director: Ivo Geilenbruegge
On 19-05-12 10:59, Pierre G. wrote:
--
Hello,
Since SWD protocol is an ARM proprietary debug protocol (at least that is my understanding).
Can we design a Riscv device - that does not contain any coresight IP - where DTM relies on SWD without any legal infringement with ARM ?
Thx in advance for your answers.
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SEGGER - Alex Gruener
May 20, 2019, 2:57:30 AM5/20/19
to Jim Wang, Pierre G., RISC-V Debug Group
Hi Jim,
I cannot really comment on ATE support for cJTAG.
We (SEGGER) are specialized in debugging and programming probes.
Round about you can say that with cJTAG you have 1/3 of the throughput at the same frequency as for JTAG.
This is because cJTAG serializes the TMS, TDI, TDO data on the same line.
So you need 3 clocks to transmit a TMS, TDI and TDO bit, where you need 1 clock at JTAG.
BR
Alex
I cannot really comment on ATE support for cJTAG.
We (SEGGER) are specialized in debugging and programming probes.
Round about you can say that with cJTAG you have 1/3 of the throughput at the same frequency as for JTAG.
This is because cJTAG serializes the TMS, TDI, TDO data on the same line.
So you need 3 clocks to transmit a TMS, TDI and TDO bit, where you need 1 clock at JTAG.
BR
Alex
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Ray Van De Walker
May 20, 2019, 5:58:40 PM5/20/19
to RISC-V Debug Group
I think the Foundation has excellent compatibility reasons to standardize a debug plug and what passes through it.
A two-wire debug protocol is handy, no doubt about it.
The hardware protocol of SWD strongly resembles a half-duplex version of SPI.
SPI is in the public domain, so why reinvent it?
A credible two-wire debug design would send RV5 abstract debug commands via half-duplex SPI, via a standard plug, with a mandatory range of voltages and frequencies.
I think that Foundation has no interests in the deeper items of a debug model: E.g. things like ARM’s DAP design, the private bus, the core interface units, bus interface units.
At most, maybe specify a way to read a ROM with something like an xml system description. Perhaps write that ROM’s description in ASN.1
Neither ROMs nor ASN.1 have IP issues.
--
SEGGER - Alex Gruener
May 21, 2019, 2:57:50 AM5/21/19
to Ray Van De Walker, RISC-V Debug Group
Hi Ray,
I get your point but can understand that vendors are looking into SWD compatibility.
It especially makes sense if hybrid devices are build that contain an ARM core and an RISC-V along with it in the same device.
It makes integration more easy as SWD is proven and used in many ARM based devices.
I can also see the need for hybrid devices for now, having RISC-V and also looking where it is developing to, at the moment.
Just my 0.02$
BR
Alex
I get your point but can understand that vendors are looking into SWD compatibility.
It especially makes sense if hybrid devices are build that contain an ARM core and an RISC-V along with it in the same device.
It makes integration more easy as SWD is proven and used in many ARM based devices.
I can also see the need for hybrid devices for now, having RISC-V and also looking where it is developing to, at the moment.
Just my 0.02$
BR
Alex
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