Debug Video Call March 8

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Megan Wachs

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Mar 7, 2017, 6:32:32 PM3/7/17
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Slides for tomorrow's 8AM PST call:


I will be logging into the call 20 mins early, please feel free to test joining earlier especially if you had trouble joining last week. 



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Megan A. Wachs
Engineer | SiFive, Inc 
300 Brannan St, Suite 403 
San Francisco, CA  94107 

Megan Wachs

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Mar 7, 2017, 7:04:53 PM3/7/17
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I sent out a new Meeting Invite for this meeting, since the old one was owned by Tim. Please update your calendars, and let me know if you did not get the meeting invite.

Thanks,
Megan

Don A. Bailey

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Mar 8, 2017, 10:33:19 AM3/8/17
to Megan Wachs, RISC-V Debug Group
Sorry for the late head's up, but I won't be able to make the call due to flu. I'd dial in anyway since I'm remote, but I have no voice to speak with. Regardless, I did write a preliminary serial-model update to the security spec. I'll clean it up and ship it to the list this afternoon once I get a bit more sleep.

I'm sure this bug won't last terribly long so I expect to be on next week's call. 

Best,

Don A. Bailey
Founder / CEO
Lab Mouse Security


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Megan Wachs

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Mar 8, 2017, 10:44:36 AM3/8/17
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黃柏瑋

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Mar 8, 2017, 12:34:03 PM3/8/17
to Megan Wachs, RISC-V Debug Group
Hi all,
Here’s my note for tonight’s meeting. 
It’s my first time to take note for debug group. Free feel to point out everything I could refine.
Thanks.
Po-wei Huang
Note start:
New comer:
Palmer-software gcc, binutils gdb
Spec
It as been moved to github RISC-V.

Enumeration and probing
On google doc
Alex- 
The item is really a lot, potentially quite a lot. 
Main interest debug soc
Need Workaround for platform without configure string,platform enumeration.
Rely on the vendor ID
OpenOCD use JTAG to ask for vendor ID but now ignore it.
How to find out current Maximum XLEN and Current XLEN?
Why do we need XLEN?
What ISA is supported 
Determine XLEN’s by running some instruction
In order to determine the size of abstract command.
Able to try and see to get the size, but is that what we wants?
Try and failed thing is ok, All specified is ok by Palmer’s Implementation

Question:
Shorter access size
Quickly determine
MID CSR from all of the hart. 
Vy:
Fundamental property of hart should be designated.
Less ambiguity is helpful.

Megan:
Not necessary to figure out
Vy:
At least some fundamental register capability ID should be specified.


Megan Wachs:
Combination or restricted.
Support for all the Hart.
Vy:
Various configuration for DM.
Subsets are optional
Almost all should be optional 
Explicitly show the region.
One register
Combination

Megan:
What is hard to decide is the abstract command
For the abstract command, we should know whether it’s failed. (Easier to implement. Make them failed.) 

Palmer:
Megan:
Don’t want to put more into the spec to find out whether this is failed.
How to determine the failed.

Do size smaller  than the maximum XLEN make sense?
We can use the MISA to determine XLEN. Long discussion….
“Can we always do a 32-bit read?

For each hart you can then just read MISA with a size = 4bits. 
MISA could change. 
Save and restore MISA in HW  (or ignore it)
Vs Save and Restore in SW
Discuss in mail.”

Alex:
Read through the list to find out which one is rechecked.

Megan:
OpenOCD didn’t cover.
Rockets chip is gaining config string.
Debug string.
Format config string.
Present of multiple bus:


Alex:
Debug module multiple bus
Debug module description 
Especially 
Standard way 

Megan:
Config string is in rocket, in the code, something like a device tree.

Simultaneous halt/resume
Megan
Needed for multiple hart system


Vy
Some need to be caught in reset.

Megan:
if an action is for hart array, it needs to be in single hart.
One hart by another.
Vy:
Different configuration/size for actions

Megan:
Did this later after other things are done.

Halt mode:
Debug mode sounds better
Make a pull request

Alex:
Discussion on trigger of virtual

Next week:
Implementation feedback

Remarkably
Give the feedback

Implementation
System bus or 
Trigger

Note end

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Megan Wachs

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Mar 8, 2017, 1:49:09 PM3/8/17
to 黃柏瑋, RISC-V Debug Group
Thanks Po Wei!



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