LVDS termination scheme to nonstandard ribbon cable
stefan....@gmail.com
I am doing a Spartan3 to Spartan 3 interconnect trough a ribbon (flat)
cable with a characteristic impedance of 173R balanced (103R
unbalanced).
I have tried xilinx webcase to answer on the termination requirements
of LVDS for spartan 3 withhout much luck. I got 2 different answers.
My questions are:
1) Can I use a ribbon cable with 173R balanced characteristic
impedance? I have read that it should be 100R. The transmission is
rather short, 300mm and relative slow in lvds terms. I would rather
not switch the cable since it have other good properities that I rely
on.
2) With the above cable should the receiver end termination still be
100R
3) With the above cable is a source resistor network necessary to
match the impedance on the transmitter side and lower reflections?
This is the point where xilinx tend to confuse itself in its
datasheets for spartan 3. My dirty solution with adding 150R series
resisor tend to give nicer signals.
Hope someone could help me on this.
Thanks in advance
Symon
news:1179994496.1...@o5g2000hsb.googlegroups.com...
> Hi
>
> I am doing a Spartan3 to Spartan 3 interconnect trough a ribbon (flat)
> cable with a characteristic impedance of 173R balanced (103R
> unbalanced).
> I have tried xilinx webcase to answer on the termination requirements
> of LVDS for spartan 3 withhout much luck. I got 2 different answers.
>
> My questions are:
>
> 1) Can I use a ribbon cable with 173R balanced characteristic
> impedance? I have read that it should be 100R. The transmission is
> rather short, 300mm and relative slow in lvds terms. I would rather
> not switch the cable since it have other good properities that I rely
> on.
>
>
> 2) With the above cable should the receiver end termination still be
> 100R
>
>
> 3) With the above cable is a source resistor network necessary to
> match the impedance on the transmitter side and lower reflections?
> This is the point where xilinx tend to confuse itself in its
> datasheets for spartan 3. My dirty solution with adding 150R series
> resisor tend to give nicer signals.
>
be no reflections.
BTW, the impedance of the cable seems high. What cable are you using, and in
what mode? I.e.
GSGSGS or GSSGSSG or has the cable got twisted pairs?
G = ground, S = signal.
Cheers, Syms.
John_H
The receiver should be the differential impedance of the cable and of
the transmitter - they should all (roughly) match. If you have an
external termination at the receiver, change it to the 173 ohm value if
that's the true differential impedance. If the termination is internal
at 100 ohms, add two 36 ohm resistors (or thereabouts) to get the
impedance match, albeit at a reduced signal amplitude.
On the transmitter, you want a 100 ohm to 173 ohm impedance match so the
transmitter sees 100 ohm but the transmission line sees 173 ohm. You'll
need a differential termination on the transmitter side of this network
and two series resistors to the ribbon cable. The signal amplitude will
again be reduced.
If the doubly-reduced signal amplitude is a problem, your slower speed
will allow a different approach. Rather than using the native 100 ohm
LVDS transmitter, step back a couple years and use a three-resistor
network to match 2.5V differential outputs to the LVDS levels and
impedances you need. If you analyze the resistor networks used by the
Bus-LVDS Xilinx I/O level or some of the older "LVDS" drivers in the
various families, you'll find simple 3-resistor networks that make the
rail-to-rail drivers look like a transmitter with 100 ohm differential
impedance with the right voltage swing. You can alter the network to
give you 173 ohms with a voltage swing appropriate to your receiver
termination.
173 ohms all the way through make the signal clean at the receiver.
Symon
news:cUg5i.9206$ix.312@trndny01...
> stefan....@gmail.com wrote:
>> Hi
>
> On the transmitter, you want a 100 ohm to 173 ohm impedance match so the
> transmitter sees 100 ohm but the transmission line sees 173 ohm. You'll
> need a differential termination on the transmitter side of this network
> and two series resistors to the ribbon cable. The signal amplitude will
> again be reduced.
>
good enough, provided the path between the driver and the cable has the same
impedance as the cable, or this path is short. Cf. ECL logic, low output
impedance, but can drive a properly terminated diff. pair. LVDS outputs are
matched to the line to get a belt 'n' braces approach to reduce reflections,
but it's not necessary to match the transmitter to the line.
Here's an app note which describes the output structures.
http://www.maxim-ic.com/appnotes.cfm/an_pk/291
HTH, Syms.
austin
I suppose suggesting that the question could be answered in less than 10
minutes using a SIGNAL INTEGRITY simulator would just be silly?
I am absolutely amazed at how much time, money, and energy is wasted
just because a SI simulator is "expensive."
One respin of a pcb is MORE $$$ than buying the SI simulator tool.
Mentor's Hyperlynx(tm) simulator is my favorite, but Cadence has their
tool which might be more to some folks liking (it is integrated with the
PCB layout stuff).
So, how about it? Invest in something that will save you enough money
to pay for it the first time you do not screw up.
Submit a hotline webcase, and ask for a "what if" SI simulation. That
way you will get a free example of (one) solution to your problem.
One comment: matching the transmitter impedance is a good idea, as a
perfect match at the receiver is impossible (perfect may happen in
textbooks, but not in real life).
Austin
austin
Xilinx must recommend the standard, tried and true, solution, we are not
allowed to cut corners, as that leads to unhappy customers and lowers
our sales figures while customers are trying to fix something they
should have gotten right the first time.
LVDS is a standard. The transmitter is 100 ohms, the line is 100 ohms,
the receiver is 100 ohms. They didn't do it this way because they were
stupid: they did it this way for the reason I stated.
If you want to do SLVDS (Symon's Low Voltage Differential Signalling) be
my guest.
Will SLVDS work? Most of the time, probably. The advantage of a
standard is "set it and forget it" as there will be no problems unless
you have done something wrong (like ignore the transmit match). Should
simulate it, though.
Another example of this is where customers discover that simple LVCMOS
works faster, and with less power to DDR SDRAM chips located close to
the FPGA. Do we recommend it? No. Do people make a robust interface,
that works just fine in production? Yes. But they have to do more
work, to make sure they will be safe across all corners (silicon,
voltage, temperature).
Austin
Symon
news:f34740$6d...@cnn.xilinx.com...
>
> One comment: matching the transmitter impedance is a good idea, as a
> perfect match at the receiver is impossible (perfect may happen in
> textbooks, but not in real life).
>
> Austin
>
example from Xilinx's own consultant's website:-
http://sigcon.com/Pubs/edn/ConstantRTermination.htm
HTH, Syms.
Symon
> Symon,
>
> Xilinx must recommend the standard, tried and true, solution, we are not
> allowed to cut corners, as that leads to unhappy customers and lowers our
> sales figures while customers are trying to fix something they should have
> gotten right the first time.
>
> LVDS is a standard. The transmitter is 100 ohms, the line is 100 ohms,
> the receiver is 100 ohms. They didn't do it this way because they were
> stupid: they did it this way for the reason I stated.
>
> If you want to do SLVDS (Symon's Low Voltage Differential Signalling) be
> my guest.
>
> Will SLVDS work? Most of the time, probably. The advantage of a standard
> is "set it and forget it" as there will be no problems unless you have
> done something wrong (like ignore the transmit match). Should simulate
> it, though.
>
>
Did you read the OP's requirement? He's not driving a 100R transmission
line, he's driving something with a different charactaristic impedance,
173R. So, the LVDS 'standard' won't work. Terminating the output will reduce
his output swing. Are you sure in this application matching the output
impedance is more important than a large signal swing?
Cheers, Syms.
p.s. Simulation is a good plan, I wonder where can you get a decent model
for ribbon cable?
austin
Yes, I know what the author of the post is trying to do.
Yes, Hyperlynx has built in models for a number of ribbon cables.
Without running the simulator, it is a complete waste of time to suggest
anything as a "solution" to this question.
Now that I have spent three times longer than I would have solving it
with the simulator, it appears that we have paid for the simulator, once
again.
GET IT? (I know you do, Symon).
Austin
Symon
news:f349ou$ppq$1...@aioe.org...
http://sigcon.com/Pubs/edn/TerminatorOne.htm
http://sigcon.com/Pubs/edn/TerminatorTwo.htm
http://sigcon.com/Pubs/edn/TerminatorThree.htm
HTH, Syms.
austin
Wrong solution.
Using the _DT internal differential termination, the driver will see 100
ohms in parallel with 5 pF (10pF in series with 10 pF).
If you SIMULATE this load, you will find that since the capacitance is
directly across the 100 ohms, the receive signal is just fine.
Any reflections are absorbed by the 100 ohm driver (gee? I wonder what
genius thought of doing this?).
The rise times from the driver are moderate, and adequate, so
mis-matches don't jump up and make life difficult, and cross talk is
reduced.
Some folks have lightning fast drivers, which cross talk like crazy, and
even their "lower" input C looks awful, as a signal with 2X the rise
makes even 3pF look really bad.
"The system is the solution." Driver, termination, line, receiver, all
have to be considered. I know, you, personally have issue with the
solution, but, face it, Virtex family has been an astounding success:
and TO THIS DAY, we are the only ones with 65nm product, shipping (at
all) production parts. ONE YEAR as of May 5th....
Think of all those sockets we are being designed into. All of those
LVDS interfaces working. Literally tens of millions of them.
Do we have room to improve? Of course. But, any improvement is
weighted against its benefits. Make the input less capacitive has no
benefit (other than you would immediately post "see! I told you!" and I
would not have to reply to this issue anymore).
What might be a better item to work on, rather than spend time on
something that "ain't broke?"
Oh, did I mention how ecstatic we are that we have a one year lead on 65nm?
Austin
John_H
> an example from Xilinx's own consultant's website:-
> http://sigcon.com/Pubs/edn/ConstantRTermination.htm
>
> HTH, Syms.
This kind of approach certainly isn't obvious.
The reflections will *certainly* be much better. Heck, the line can be
probed and a good signal seen just about anywhere along the transmission
line (assuming the probe doesn't introduce problems).
What should be noted is that - while there are no reflections and the end of
the transmission line will see a superb voltage slow thanks to the R-only
termination, this clean transition sees a series Zo impedance between it and
the capacitor.
For a standard parallel Zo termination to a Zo characteristic impedance
transmission line, the effective source is half the drive voltage through a
Zo/2 impedance into the capacitor. If there is no capacitance, the
transition is gorgeous at the receiver.
For the termination scheme suggested, the point where the transition line
sees the resistance is the same half-voltage swing. Trouble here is that
the equivalent series impedance to the capacitor is no longer fed by a half
voltage with Zo/2 equivalent series impedance, but now a half voltage with a
Zo series impedance.
If it's important to not have reflections, the R-only equivalent termination
is superb.
If it's important to have the high slew rate, the standard termination with
the associated pin capacitance is the way to go because the reflection
*will* be absorbed by the transmitter's impedance if it's properly matched.
Signal Integrity *at the pin* is what's important and where a monte-carlo SI
analysis will show which approach provides a cleaner interface in the end.
For this implementation where the speed is low, the extra 250 ps of RC time
constant (it's C/2 for a differential signal) will probably provide
excellent results.
- John_H
John_H
<snip>
> Without running the simulator, it is a complete waste of time to suggest
> anything as a "solution" to this question.
No need to get <snip>py. There were many successful high speed designs
before SI got the usable, affordable tools available today. Without a
fundamental understanding of what DOES affect signal fidelity, we doom our
engineering future to shotgun hacks at "trying" to get the signals to
perform well.
Since we have the SI tools available now in a way they weren't available a
decade ago, quick analysis of alternatives can be pursued. To suggest that
fundamental knowledge be tossed out since there's a tool available is the
short-sided view that often comes with the frustration of trying to
communicate your point.
Please don't ask engineers to avoid learning the basics of delivering good
signal integrity just because the tools are available to avoid doing the
heavy mental lifting. When's the last time you gave someone $22 for a $17
charge expecting to get a $5 bill back and they stare at you like you're
nuts. "But it's only $17." The crutch of calculators and cash registers
have crippled much of a generation. Lets keep engineering steeped in
fundamentals and use the tools as they're meant: as tools.
- John_H
Symon
Hi Austin,
I do so enjoy our little chats! I also know that you're a big fan of
simulation, and I totally agree it's a great tool. (Oh, and BTW, thanks for
the pointer, I didn't realise that some ribbon cables were included in
Hyperlynx, that's cool! Although, I fear the OP's cable is not included.)
My only comment is that some people are actually interested in the
mechanisms at work. I'd say it's important to learn that first, and then use
the simulator.
All the best, Syms.
Symon
> Symon,
>
> Wrong solution.
>
> Using the _DT internal differential termination, the driver will see 100
> ohms in parallel with 5 pF (10pF in series with 10 pF).
>
> If you SIMULATE this load, you will find that since the capacitance is
> directly across the 100 ohms, the receive signal is just fine.
>
> Any reflections are absorbed by the 100 ohm driver (gee? I wonder what
> genius thought of doing this?).
>
the line from a S3. So the 100 ohm driver has 5pf across it. Oh dear, the
same reflection mechanism as at the receiver!
>
> The rise times from the driver are moderate, and adequate, so mis-matches
> don't jump up and make life difficult, and cross talk is reduced.
>
good thing, no matter how you spin it! It's only adequate if your
application needs a moderate rise time!?
>
> Some folks have lightning fast drivers, which cross talk like crazy, and
> even their "lower" input C looks awful, as a signal with 2X the rise makes
> even 3pF look really bad.
>
to the drivers, you make it sound such a great idea! (Apologies for the
sarcasm)
>
> "The system is the solution." Driver, termination, line, receiver, all
> have to be considered. I know, you, personally have issue with the
> solution, but, face it, Virtex family has been an astounding success: and
> TO THIS DAY, we are the only ones with 65nm product, shipping (at all)
> production parts. ONE YEAR as of May 5th....
>
> Think of all those sockets we are being designed into. All of those LVDS
> interfaces working. Literally tens of millions of them.
>
> Do we have room to improve? Of course. But, any improvement is weighted
> against its benefits. Make the input less capacitive has no benefit
> (other than you would immediately post "see! I told you!" and I would not
> have to reply to this issue anymore).
>
> What might be a better item to work on, rather than spend time on
> something that "ain't broke?"
>
> Oh, did I mention how ecstatic we are that we have a one year lead on
> 65nm?
>
> Austin
Wow, what brought that on? I'm sorry but for some reason I kept seeing Tom
Cruise on the couch when I was reading that! Ever thought of switching to
de-caf? :-) (Just kidding!!) Anyway, we've been through this before, we're
never gonna agree, your loyalty to Xilinx is too strong for that (kidding
again!), but anyone who's interested can search back through comp.arch.fpga
and decide for themselves whether high speed outputs and receivers are
compromised by pin capacitance.
Cheers, Syms.
Symon
> "Symon" <symon_...@hotmail.com> wrote in message
> news:f349ou$ppq$1...@aioe.org...
>>>
>> It is possible to match even Xilinx's hideous 10pF receiver pins. Here's
>> an example from Xilinx's own consultant's website:-
>> http://sigcon.com/Pubs/edn/ConstantRTermination.htm
>>
>> HTH, Syms.
>
>
> termination is superb.
> If it's important to have the high slew rate, the standard termination
> with the associated pin capacitance is the way to go because the
> reflection *will* be absorbed by the transmitter's impedance if it's
> properly matched.
>
> Signal Integrity *at the pin* is what's important and where a monte-carlo
> SI analysis will show which approach provides a cleaner interface in the
> end.
>
> For this implementation where the speed is low, the extra 250 ps of RC
> time constant (it's C/2 for a differential signal) will probably provide
> excellent results.
>
> - John_H
>
Neatly summarised!
Thanks, Syms.
austin
We agree to disagree.
I would hope that it is clear that the Xilinx solution works just fine.
There are just far too many working pcbs out there to suggest otherwise.
I have already agreed it could be better, but if it works, why bother?
As for loyalty to Xilinx, I am trying to be an engineer: facts, facts,
facts.
Fact: input Z (and output Z) = 100 ohms + 5pf
Fact: risetime is adequate for the job (too fast is actually a bad
thing, too slow just mens you can't operate at very high rates, parts
meet their specifications)
Fact: Symon hates having any C in parallel with the termination.
Fact: All terminations have some C.
Fact: Symon and I do not agree.
Austin
austin
I agree. For those for whom SI is a mystery, learn something today: go
read up on SI.
Austin
austin
In no way did I imply that engineers should not learn about SI.
But, I can not require SI knowledge, either.
That is why we have IO standards (cookbook recipes).
Without a degree in E&M theory, I would argue that you can't really
understand what is going on.
Well, a suppose a physicist might be capable of recognizing Maxwell's
equations, but as far as I know, only those who have actually set up,
and solved these equations, have the fundamental knowledge that is required.
There are many who have practical knowledge (experience), and that
sometimes passes for understanding.
Anyone else is someone who is just pretending they have the knowledge.
And that is just fine: just as we can not ask that all users of FPGAs
know everything about heat transfer, we recognize that the team who are
using the FPGA will require some support for those specialties that they
lack.
Austin
John Larkin
Does an LVDS transmitter have an impedance? The ones I've played with
seem to behave like current sources; unloaded, the diff outputs swing
(slowly!) almost rail-to-rail. That said, presenting the transmitter
with an equivalent 100 ohm net diff load will normalize the swing to
standard levels and speed things up a bit as compared to letting them
see a 173 or whatever diff load.
John
John Larkin
wrote:
National's CMOS structure is different,
http://www.national.com/appinfo/lvds/files/lvds_ch1.pdf
more of a real current source. I'd guess that the Maxim is the oddball
here. The National and Fairchild transmitters I've played with will go
rail-to-rail if not terminated. I haven't tried an unterminated Xilinx
lvds driver; their receivers are pretty good r-r comparators.
John
John_H
news:0ppb531bd38oj99t3...@4ax.com...
>
> National's CMOS structure is different,
>
> http://www.national.com/appinfo/lvds/files/lvds_ch1.pdf
>
> more of a real current source. I'd guess that the Maxim is the oddball
> here. The National and Fairchild transmitters I've played with will go
> rail-to-rail if not terminated. I haven't tried an unterminated Xilinx
> lvds driver; their receivers are pretty good r-r comparators.
>
> John
The FPGA structures appear to be what are important to this conversation.
There are transmitters that are true current sources both with and without
internal 100 ohm parallel terminations. There are transmitters that present
voltage drivers with (series) source impedances that roughly match the
current-source approach.
For anyone designing with LVDS, appropriate reading of the data sheet
information on the transmitter is important. For a proper LVDS connection,
the transmitter needs to appear to be a 100 ohm differential source.
Different manufacturers are happy to deviate slightly from the originally
proposed driver structure to present something with equivalent
characteristics when properly configured whether this means plug&play, an
external parallel termination, or a 3-resistor network to "look" like the
equivalent source. Without the 100 ohm equivalent transmit impedance, any
reflections from the receiver or other impedance mismatches will reflect
back toward the receiver rather than be absorbed at the source.
- John_H
austin
The LVDS standard specifies that the transmitter has a 100 ohm resistive
termination to absorb reflections.
Austin
John_H
> John [Larkin],
>
> The LVDS standard specifies that the transmitter has a 100 ohm resistive
> termination to absorb reflections.
>
> Austin
Some LVDS transmitters have no (design) impedance. This is what I [John_H]
was referring to in another post. Those transmitters that are implemented
as current sources require that the transmitter have the differential
impedance required to absorb the reflections from the LVDS line and
receiver.
The transmitter data should always be referenced to make sure the impedance
is integrated into the transmitter, is required externally, or if the driver
needs to be "transformed" to an equivalent source such as the Xilinx BLVDS.
- John_H
John Larkin
<news...@johnhandwork.com> wrote:
>"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> wrote in message
>news:0ppb531bd38oj99t3...@4ax.com...
>>
>> National's CMOS structure is different,
>>
>> http://www.national.com/appinfo/lvds/files/lvds_ch1.pdf
>>
>> more of a real current source. I'd guess that the Maxim is the oddball
>> here. The National and Fairchild transmitters I've played with will go
>> rail-to-rail if not terminated. I haven't tried an unterminated Xilinx
>> lvds driver; their receivers are pretty good r-r comparators.
>>
>> John
>
>The FPGA structures appear to be what are important to this conversation.
>There are transmitters that are true current sources both with and without
>internal 100 ohm parallel terminations. There are transmitters that present
>voltage drivers with (series) source impedances that roughly match the
>current-source approach.
>
>For anyone designing with LVDS, appropriate reading of the data sheet
>information on the transmitter is important. For a proper LVDS connection,
>the transmitter needs to appear to be a 100 ohm differential source.
Everywhere I look, I see unterminated transmitters:
http://zone.ni.com/devzone/cda/tut/p/id/4441
http://www.interfacebus.com/Design_Connector_RS644.html
http://www.fairchildsemi.com/ms/MS/MS-547.pdf
http://www.ams.aeroflex.com/ProductFiles/Presentations/LVDSOverview9-04.pdf
http://spacewire.esa.int/content/TechPapers/documents/SpaceWire%20Standard%20%20ISWS%202003.pdf
This makes sense: a 3.5 mA current source (transmitter) drops the
proper 350 mV across the 100 ohm receive termination. If the
transmitter also terminated in 100 ohms, you'd net half that swing.
That's consistant with my observation that unterminated transmitters
slew rail-to-rail on both pins.
>Different manufacturers are happy to deviate slightly from the originally
>proposed driver structure to present something with equivalent
>characteristics when properly configured whether this means plug&play, an
>external parallel termination, or a 3-resistor network to "look" like the
>equivalent source. Without the 100 ohm equivalent transmit impedance, any
>reflections from the receiver or other impedance mismatches will reflect
>back toward the receiver rather than be absorbed at the source.
But if the receiver terminates properly, there will be no reflections.
John
Symon
Have a look at the link I posted yesterday. This one:-
http://www.maxim-ic.com/appnotes.cfm/an_pk/291
It shows the output structure for LVDS. The (12mA) current source has high
impedance, so the output impedance is determined by the resistors show. I
think the LVDS transmitters you mention must have some other type of
structure. Can you post what they were?
HTH, Syms.
Symon
> "John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> wrote in
> message news:u4pb535aii2c97o28...@4ax.com...
>>
> Have a look at the link I posted yesterday. This one:-
> http://www.maxim-ic.com/appnotes.cfm/an_pk/291
> It shows the output structure for LVDS. The (12mA) current source has high
> impedance, so the output impedance is determined by the resistors show. I
> think the LVDS transmitters you mention must have some other type of
> structure. Can you post what they were?
> HTH, Syms.
>
>
Cheers, Syms.
Symon
Right. My point exactly.
Also, many thanks for those links, looks like I found, and posted a link to,
the only manufacturer that shows LVDS outputs including the resistors.
However, if you revisit the pictures in your links, I think you'll see that
they paint a simplified picture. If you go to the National link you posted,
it's clear that the lower MOSFET isn't just a short to ground when it's on.
Otherwise the device would not be meeting the output common mode voltage
spec. There's maybe(?) a resistor in there somewhere, and this provides the
required output impedance. The Analog device links show a current source top
& bottom, which would suggest the Vcm could be anywhere.
So, I think we need to view these diagrams as not the full picture. However,
I agree with you that it seems most manufacturers aren't all that concerned
with output impedance, which is interesting.
Cheers, Syms.
austin
I agree. (Twice? I must be slacking...)
To meet the IEEE/ANSI specification, there is a transmit termination.
If not internal, it would be specified as external.
If not shown, it still may be present.
Diagrams in data sheets are often simplified.
Austin
John Larkin
wrote:
Yup, the common-mode setting thing is an obvious omission.
John
stefan....@gmail.com
I have been away on an urgent business trip, so I have not been able
to watch the replies before now.
Below are answers for posts that I find I could reply back to and in
the same order as the postings.
Symon:
Yes the impedance is high (if the supplier given numbers for
unbalanced and balanced impedance apply).
It is a 0.50 pitch flexible flat cable used in the configuration
GPNGPNG where P is positive part and N inverted signal.
John H:
Your solution looks promising and to some degree as my first mock-up
trial.
The reduced swing should not be a problem, as long as it does not
alter the signal to much to my low-speed application.
Austin:
You are right. But it should also be possible to do without in a low
speed LVDS scenario.
And we are looking into buying Hyperlynx....But the SI's weak point is
that you should know the correct properties of your whole path.
Thanks for your comment regarding the transmitter matching.
I have requested a Hyperlynx eval license, then it is just the whether
I am able to use it straightaway to simulate LVDS pairs:-)
And as the others said earlier, I wanted some feedback before trying
Hyperlynx, since I would need an idea of what to simulate, since
Xilinx only mention the need for Receiver diff termination.
Thanks again for all of your.
austin
You are welcome.
Out of the box evaluation version may not have all the features, but it
will be useful. What is included: some ribbon cables, coax, etc. PCB
trace configurations for stripline, micro-strip, etc. Connectors. The
linsim package will extract from layout to check that your PCB is OK
before you fabricate it.
Slow enough speed, and SI is pretty much a "don't care" except for
things like SSO (which LVDS has no restrictions on).
Austin
Brian Davis
>
> If it's important to not have reflections, the R-only equivalent
> termination is superb.
>
> If it's important to have the high slew rate, the standard
> termination with the associated pin capacitance is the way to go
> because the reflection *will* be absorbed by the transmitter's
> impedance if it's properly matched.
>
a T-coil termination network theoretically could both peak the load
AND terminate the line all in one fell swoop.
I posted about this on the si-list last year, and one of the
Teraspeed guys provided some more T-coil references:
http://www.freelists.org/archives/si-list/03-2006/msg00153.html
http://www.freelists.org/archives/si-list/03-2006/msg00162.html
I've considered this impractical at the board level with wide
LVDS buses, but the T-coil papers make for fun reading nonetheless!
>
> If it's important to have the high slew rate, the standard
> termination with the associated pin capacitance is the way to go
> because the reflection *will* be absorbed by the transmitter's
> impedance if it's properly matched.
>
At the 1 Gbps rates claimed by Xilinx, the typical Rx Cin of
~10 pf (single ended) [Note 1] often presents difficulties that
need to be addressed during the board design phase, particularly
when using fast drivers from other logic families.
IIRC, the 500 Mbps 1995 ANSI LVDS spec called out:
output swing: 250 mV min differential
source impedance: 40-140 ohm single ended
termination impedance: 90-110 ohms differential
driver rise/fall time: 300 ps min, 500 ps max
Even within the range of allowed values for this old, slow spec,
a 300 ps edge WILL reflect off of the 10 pF Cin (single ended)
of a Xilinx pin, and then subsequently re-reflect off any
80-280 ohm (differential) impedance mismatch at the driver.
Later, faster specs such as HyperTransport tighten these
requirements even more to help deal with the faster edges
of a 1 Gbps driver.
Despite newsgroup claims that Xilinx parts "meet all specs
and standards", they do not in fact meet many of the Cin, Rdiff,
rise/fall, and even Vod (in S3) of the relevant standards for
the claimed input data rates.
Xilinx _DT input terminations are 100 ohm +/-20%, or worse,
depending upon family and common mode input voltage [Note 2].
Brian
Note 1: Cin (single ended) vs. Cin (differential)
If the input signal is perfectly differential, the reflections
will be IDENTICAL regardless of whether input C is modeled as
two 10 pf shunt Cin (as specified in both the datasheet and
the IBIS models) or as one 5 pf Cdiff.
Calling it 5 pF doesn't make the parts work any better.
If the input signal is NOT perfectly differential, the
10 + 10 = 5 simplification does not apply.
Note 2:
The _DT terminators seem to be implemented using FETs,
producing a bowed termination curve that is near 100 ohms
only when Vicm is somewhere near the output driver's
specified Vocm.
The actual Rdt value varies family to family, and changes
with VCCO and Vicm.
Measurements of a sample-of-one FX12 LVDS_25_DT,
at nominal 2.5V VCCO supply, at room temp:
Vicm Rdt
-----------------------
0.50 V ~ 74 ohms
0.75 V ~ 78 ohms
1.00 V ~ 94 ohms
1.25 V ~ 125 ohms
1.50 V ~ 157 ohms
using a 7CT1N curve tracer with two 100 ohm
series R's to reduce Vdiff to about Vin/3
Sweeping Vin 0-3V => Vicm 0-1.5V
:
: 7CT1N + ----/\/\-----
: 100 |
: /
: Vin \ Rdt
: /
: |
: 7CT1N - ----/\/\-----
: 100
John_H
Brian, I always appreciate a well-considered discussion and hope to look
at the T-coil references. Beyond these references I don't know that the
rest of the discussion does much more than stir the bees nest though I
do also appreciate the perspective from the curve tracer.
Austin, I'm sure you want to retort. Could you let this one go by
without a response? It's feeling old.
- John_H
Brian Davis
>
> Brian, I always appreciate a well-considered discussion and hope to look
> at the T-coil references. Beyond these references I don't know that the
> rest of the discussion does much more than stir the bees nest though I
> do also appreciate the perspective from the curve tracer.
>
perfectly balanced with ideal back terminations, then best of luck
with
your high speed designs; somehow, I suspect you are more pragmatic.
>
> Austin, I'm sure you want to retort. Could you let this one go by
> without a response? It's feeling old.
>
What I find old is vendor employees continuing to make known
false or misleading claims like "(We) meet all specs and standards",
"Cin doesn't matter", and "but it's really Cin/2".
If I occasionally point out the real-world issues on a thread where
the subject comes up, it's only after I've counted slowly backwards
from 200 by two's and deleted most of my original response.
Brian
John_H
Cin matters but - in a properly designed system - it doesn't matter so
much. If the impedances in the system - source, transmission line,
receiver - are crap, then the C will have a huge impact. Since the
transmitters will tend to have high C as well in Xilinx transmitters,
reflections should be expected.
One thing you appear to rely on from previous posts is probing of the
signal at a point external to the receiver silicon, the only place
practical to probe. This will always result in a signal that's worse
than the actual received signal when high Cs (or other impedance
mismatches) are involved.
Since these are digital systems, *some* reflections are acceptable.
Having a signal without extremely well defined highs and lows are
typically acceptable. The impact on the time-domain is where the
interference will often be noted the most and transmission systems with
much better analog performance (including the C and R termination
values) are required to maintain a low phase noise.
It really is C/2 for those who are thinking 100 ohm impedance. It
really is C for those who are thinking 50 ohm impedance. Where are
peoples' minds normally on the impedance for LVDS? There are no lies here.
I've been impressed with an engineer's approach within my own company to
try to reduce common-mode artifacts and EMC issues by filtering from the
midpoint of the differential termination. It becomes less obvious why a
well-matched C value is so critical when his termination scheme is
scrutinized. I was impressed.
Your real-world issues are flavored by the way you observe your system.
The SI results will often provide much better response than your
practical observations. That appears to be a thorn in Austin's side in
the same way his C/2 "claims" are a thorn in yours.
I have always found your responses to be well considered and sincerely
appreciate your self-editing: a rare talent on a forum like this.
While you may hate the impairments induced by the LVDS transceivers that
are hampered by a design that supports multiple I/O standards, it
impresses the hell out of me just how open the data eyes are in the
chip. Take a sample of your high-speed data with a carry-chain as a
delay element and accumulate. You'll see how good or bad the
time-domain is. You can futz with the common-mode, add an offset to the
differential, or reduce the transmitter swing to see when and how this
eye starts to break down.
I love that a 600 Mbit link in the "cheap" S3E devices hampered not by
one but by TWO DCMs can result in an eye that's still half open; I could
blame just about all of that mess on the DCMs, not the LVDS transceivers.
- John_H
austin
No, I am tied of the ranting. Fact is, it works.
Also, there were some customers that had really bad experiences trying
to make their boards work.
Far be it from me to suggest that these folks did something wrong, but I
have to wonder why other customers have this working.
All I can say is that we have demo boards, with network interfaces,
running at DDR rates of 800 Mbs, and on V5, at 1 Gbs. So, it is more
than a data sheet claim, it is working, proven across PVT, with HDL
code; solutions.
Austin
Brian Davis
>
> No, I am tied of the ranting.
>
>
> Also, there were some customers that had really bad experiences trying
> to make their boards work.
>
> Far be it from me to suggest that these folks did something wrong,
> but I have to wonder why other customers have this working.
>
My boards work great, because I know when and how to be cautious
when driving FPGA inputs from fast logic.
When's the last time YOU actually designed a PCB?
The boards I've had problems with have been various
Xilinx sanctioned "high speed" boards, with terminators
hanging off big stubs, or similar mistakes [1].
>
> All I can say is that we have demo boards, with network interfaces,
> running at DDR rates of 800 Mbs, and on V5, at 1 Gbs. So, it is more
> than a data sheet claim, it is working, proven across PVT, with HDL
> code; solutions.
>
But where are your simulations and real-world test data [2] ?
Take a look at XAPP774 and the associated board schematics
for TI's ADS5273 EVB combo <sbau091.pdf> and <sbau093a.pdf>
Where are the IBIS sims or real-world plots of input signal
timing and margin when driving the FPGA?
As I pointed out last spring, driving 10 pF Cin from an
ADS5273 without back termination is a recipe for disaster [3].
And if you ever have the technical integrity to post a link
to your 'works fine' IBIS simulation, I'd be happy to explain
the mistakes you made when you penned these nasty remarks [4]:
>
> I don't know about anyone else, but it works fine, and posts
> like this of sims poorly done are not helpful to anyone.
>
> I am sorry I took your posting seriously enough to do a real
> simulation and show that there is no problem (which I knew
> already from the customers that are using our parts successfully).
>
Brian
[1] Big stubs on ML450 HyperTransport interface
http://groups.google.com/group/comp.arch.fpga/msg/3654e1982a62ea81
[2] V4 thread looking for real-world measurements
http://groups.google.com/group/comp.arch.fpga/msg/3dc2fc501b48d9b7
[3] updated ADS5273 simulation, IBIS vs. simple SPICE model
http://groups.google.com/group/comp.arch.fpga/msg/5a8720eec942612e
[4] Austin's attacks on my ADS5273 simulation
http://groups.google.com/group/comp.arch.fpga/msg/33e48c977fa78001
http://groups.google.com/group/comp.arch.fpga/msg/6b33bab4a35999bf
Symon
news:1180632225.1...@h2g2000hsg.googlegroups.com...
> Austin wrote:
>>
>> No, I am tied of the ranting.
>>
> And I am tired of your marketing misdirections.
>
>>
>> Also, there were some customers that had really bad experiences trying
>> to make their boards work.
>>
>> Far be it from me to suggest that these folks did something wrong,
>> but I have to wonder why other customers have this working.
>>
> My boards work great, because I know when and how to be cautious
> when driving FPGA inputs from fast logic.
>
experiences(whether good or bad).
It seems to me that we all know _why_ the pins have high capacitance. It's
because the chips are a compromise to work with many different I/O
standards. Some of these standards require big FETs with high capacitance.
That's fair enough, I'm sure FPGA vendors spend a lot of time and effort on
marketing research and know that this is the best mix.
However, I share Brian's frustration when it's implied that the Cpin is a
'good thing' because, for example, "cross talk is reduced". Not powering the
part is another way to reduce crosstalk, and only a little less practical.
Why not just say why the Cpin is 10pF, when this matters, and how to deal
with the (hopefully few) cases where it may be a problem? IMO, this would be
better than denying the problem exists at all. Indeed, this is the approach
of this guy, who I believe consults for Xilinx.
http://sigcon.com/Pubs/edn/TerminatorOne.htm (Look at the figure, is he
timing 8ns with an egg timer? :-)
http://sigcon.com/Pubs/edn/TerminatorTwo.htm
http://sigcon.com/Pubs/edn/TerminatorThree.htm
In summary, nobody expects FPGA parts to be the best at everything, and it's
important to be careful when designing at the limits of performance.
Best regards, Symon.
p.s. God only knows what the OP thinks of this thread! I hope we haven't
scared him off for good! :-)
austin
I do SI simulations almost daily. I review PCB designs almost weekly.
All boards get built.
That is ~ 50 pcbs a year.
Many of them for people like C****, A******-L*****, N*****, F******,
N**, S***. They ask my shop to confirm that they will have a working
pcb when they get it back, and I am happy to help them out. That way,
the parts go on, the next order is received, and we sail into
qualification, testing, and production release. I just love big orders
for parts.
I also get to see every pcb that fails SI, for any reason. And, I am
often required to find the solution to fix it (which as you know can be
impossible once the board is fabricated to fix anything).
Customers are not shy when it comes to complaining when something
doesn't work. When I go to Xilinx, we had 0 SI experts working for us.
We now have SI people on the hotline, SI people in the applications
group, SI people in the packaging group, SI people in the IO group, SI
people in the field offices, SI FAE's, the RocketLabs facilities. Who
do you think planned this all out, and created the system? I am bored
by SI challenges, and I made sure there were trained experts who enjoyed
SI challenges for customer support, so I can move on to things that are
more fun (like the cases they couldn't solve).
There are numerous pcbs that Xilinx makes for characterization, testing,
SEU, signal integrity package validation, etc. I have to do the SI on
them with my team, which also has a top notch SI engineer on it. My pcb
designer did microwave radios for years and years. He solves wave
equations in his head naturally (it is scary!).
Do I qualify per your criteria? Does having (and using) my
undergraduate degree in E&M theory enable me to say something? Is 31
years designing real products that people buy, mean anything to you?
Just agree to disagree, and drop it. OK?
Or, you agree that we are both a**h****, and just move on?
Either is fine with me.
Austin
Jim Granville
> However, I share Brian's frustration when it's implied that the Cpin is a
> 'good thing' because, for example, "cross talk is reduced". Not powering the
> part is another way to reduce crosstalk, and only a little less practical.
:)
>
> http://sigcon.com/Pubs/edn/TerminatorOne.htm (Look at the figure, is he
> timing 8ns with an egg timer? :-)
Yup, the original 'silicon chips' timer ;)
-jg
Brian Davis
>
>Since the transmitters will tend to have high C as well
> in Xilinx transmitters, reflections should be expected.
>
much easier to deal with.
My posts cautioning about Cin have always been in the context
of a fast, non-FPGA driver (LVDS, LVDS-ish, ECL, etc. ) into
a FPGA input with big Cin.
When the thread discussion turned to external matching
networks for ECL drivers, I thought the T-coil Cin
matching scheme would be of interest.
>
> One thing you appear to rely on from previous posts is probing
> of the signal at a point external to the receiver silicon, the
> only place practical to probe. This will always result in a
> signal that's worse than the actual received signal when high
> Cs (or other impedance mismatches) are involved.
> <snip>
> The SI results will often provide much better response than your
> practical observations.
>
I use lab measurements to verify my simple first or second
order SPICE simulation models at the points I CAN observe,
after which I can then experiment in simulation with some
comfort of reality being conserved at the receiver input.
I 'forward' clock and test signals on/off chip using
LVDS DIFF_OUT buffers and OFDDR's, letting me measure
clock distribution without the need for a DCM.
A mechanical trombone line allows an internal sample clock
to be offset without any need to worry about DCM jitter or
other on-chip delay techniques.
Tek probes of 15-20 years ago in the form of an SD-14
or P6150 (with bias offset), on an 1180x or CSA803 sampler,
can easily measure 1 Gbps LVDS, with minimal loading impact,
and are practically free since the dot com telecom bust.
Note that sometimes my use of the word "probe" is intended in
the context of "bus probe", in which case the external probe
is capturing and analyzing the bus traffic- this requires the
reflections be damped or otherwise equalized at the point
of probe attachment so that the sample clock is usable.
>
> It really is C/2 for those who are thinking 100 ohm impedance.
> It really is C for those who are thinking 50 ohm impedance.
> Where are peoples' minds normally on the impedance for LVDS?
> There are no lies here.
>
When I say "10 pf Cin (single ended)", I am specifically
referencing Xilinx's only datasheet spec for capacitance,
called Cin, which is a single-ended specification.
I have pointed this out to Austin numerous times, yet he
still insists on "correcting" ( his term ) any references
to Xilinx's published Cin values, even after I started
explicitly postfixing the '(single ended)' whenever I
reference Cin.
My references to C_COMP and C_PKG are also, like their
IBIS values, single ended.
I am loath to quote the calculation Cin/2 instead of the
actual specification values because :
1) It's only valid if the input is perfectly differential
2) A more realistic input model includes pin-pin capacitance
separately as Cdiff, giving a calculated total differential
capacitance Ccalc = Cdiff + Cin/2
IIRC, one of the IBIS summit papers discussed LVDS modeling
using a C_DIFF, C_PKG, and C_IN, but I can't turn up the
paper just now.
>
> I love that a 600 Mbit link in the "cheap" S3E devices
> hampered not by one but by TWO DCMs can result in an eye
> that's still half open; I could blame just about all of
> that mess on the DCMs, not the LVDS transceivers.
>
I also think the S3E's are great.
C_PKG + C_COMP ~= 3 pf, $$ < 10, at quantity 1 in VQ100
Brian
Brian Davis
of an original S3 family device ( not E,A,AN,... )
John_H wrote:
>
> The receiver should be the differential impedance of the cable and of
> the transmitter - they should all (roughly) match. If you have an
> external termination at the receiver, change it to the 173 ohm value if
> that's the true differential impedance. If the termination is internal
> at 100 ohms, add two 36 ohm resistors (or thereabouts) to get the
> impedance match, albeit at a reduced signal amplitude.
>
If this is an original Spartan-3, the differential terminations
are not available, so external terminations will be needed.
Put them as close to the package as you can, especially for any
clock or strobe signals.
>
> On the transmitter, you want a 100 ohm to 173 ohm impedance match so the
> transmitter sees 100 ohm but the transmission line sees 173 ohm. You'll
> need a differential termination on the transmitter side of this network
> and two series resistors to the ribbon cable. The signal amplitude will
> again be reduced.
>
Here, I'd suggest a switch to the LDT output standard instead
of LVDS, which will give you higher minimum drive and will help
make up for the lower output amplitude caused by the series
matching resistors.
I'd normally suggest using LVDS_EXT, another variant of LVDS
with extra drive, but in the original S3, the differential
output specs are a bit odd, with Vod(min) of only 100 mV for
both LVDS and LVDS_EXT, unless you have a certain mask revision.
( See table 37 of DS099 v2.2 )
As you are going FPGA to FPGA, you can switch the I/O standards
on both ends, but watch the change in SSO limits for the various
differential standards ( See table 49 of DS099 v2.2 )
Brian