Update: Simple ADS5273 -> Xilinx Interconnect Model

[Brian Davis]

Following up on an older thread:
http://www.fpga-faq.org/archives/97450.html#97451

http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/84104bcc0cbd0ff1

Thanks to everyone who posted or emailed with suggestions, or
just to say they found those notes helpful.

I've updated that earlier file with PRBS eye diagrams, alternate
termination schemes, comparison with IBIS models, and notes
on probes and probe loading:

http://members.aol.com/fpgastuff/lvds_current.pdf
http://members.aol.com/fpgastuff/lvds_current.zip

Brian