Virtex4 PPC405 FPU problem
FreeRTOS.org
Hi,
I have a working PPC405 design to which I want to add the APU FPU IP (enough
acronyms?). I have used the wizard to configure basically the same design,
but with the FPU included - this is therefore the default wizard hardware
design with no manual tinkering from me on either the hardware or software
libraries. This now runs non floating point instructions but generates
program exceptions when an FPU instruction is executed.
Looking at the PPC405 block reference guide I am informed that I have to set
bits 6 (APU present) and 18 (FCM floating point unit present) in the MSR
register of the PPC405 in order for the APU to intercept the FPU
instructions - but the PPC405 reference guide from Xilinx states that all
these bits are unsupported and must be set to 0. This seems contradictory.
Any advice on how to add the APU FPU unit to a PPC405 design without FPU
instructions generating exceptions would be gratefully received!
--
Regards,
Richard.
+ http://www.FreeRTOS.org
17 official architecture ports, more than 5000 downloads per month.
Didi
> ...
> Looking at the PPC405 block reference guide I am informed that I have to set
> bits 6 (APU present) and 18 (FCM floating point unit present) in the MSR
> register of the PPC405 in order for the APU to intercept the FPU
> instructions - but the PPC405 reference guide from Xilinx states that all
> these bits are unsupported and must be set to 0. This seems contradictory.
I would read that as "there is no FPU with that core". But I am not
familiar
with the PPC implementation of Xilinx, I remember once I rejected the
405 for a design because of the too long errata sheet it had after
many years
on the market (still the case, I believe).
Dimiter
------------------------------------------------------
Dimiter Popoff Transgalactic Instruments
http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/
Original message: http://groups.google.com/group/comp.arch.embedded/msg/4d9148a93361cce1?dmode=source
FreeRTOS.org
> familiar
> with the PPC implementation of Xilinx,
That is correct - there is no built in FPU and no support from the core
itself. The FPU is a separate peripheral that communicates with the PPC
through the APU (Auxillary Processor Unit?).
--
Regards,
Richard.
+ http://www.FreeRTOS.org & http://www.FreeRTOS.org/shop
17 official architecture ports, more than 5000 downloads per month.
+ http://www.SafeRTOS.com
Certified by TÜV as meeting the requirements for safety related systems.
Didi
> > I would read that as "there is no FPU with that core". But I am not
> > familiar
> > with the PPC implementation of Xilinx,
>
>
> That is correct - there is no built in FPU and no support from the core
> itself. The FPU is a separate peripheral that communicates with the PPC
> through the APU (Auxillary Processor Unit?).
>
Well then the MSR bits bear no relationship to it, they apply to the
FPU described in the PPC architecture books. I have not used any
APU with a PPC, but they have no "coprocessor interfeace" defined
as it used to be on the 68020 and CPU32, it is either accessed through
some instruction set extensions or as a plain peripheral. I would be
surprised if it runs the standard PPC FPU opcodes, makes no sense
since it cannot be switched on/off via the MSR.
Dimiter
------------------------------------------------------
Dimiter Popoff Transgalactic Instruments
http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/
Original message: http://groups.google.com/group/comp.arch.embedded/msg/decf1fcf535dde0f?dmode=source
Matthew Hicks
and the Virtex-4FX, but the V2P doesn't have the ability to use the APU.
Maybe the part you read that talk about the bits being unsupported were
talking about the V2P. I was looking into building a module and attaching
it via the co-processor bus, but alas, I have a V2P. Good luck, it looks
complicated.
---Matthew Hicks
> ML403 - Virtex4 - PPC405 - Xilinx EDK V10.1
>
> Hi,
>
> I have a working PPC405 design to which I want to add the APU FPU IP
> (enough acronyms?). I have used the wizard to configure basically the
> same design, but with the FPU included - this is therefore the default
> wizard hardware design with no manual tinkering from me on either the
> hardware or software libraries. This now runs non floating point
> instructions but generates program exceptions when an FPU instruction
> is executed.
>
> Looking at the PPC405 block reference guide I am informed that I have
> to set bits 6 (APU present) and 18 (FCM floating point unit present)
> in the MSR register of the PPC405 in order for the APU to intercept
> the FPU instructions - but the PPC405 reference guide from Xilinx
> states that all these bits are unsupported and must be set to 0. This
> seems contradictory.
>
> Any advice on how to add the APU FPU unit to a PPC405 design without
> FPU instructions generating exceptions would be gratefully received!
>
andrew....@softhome.net
The UG11's tbl 4-1 indicates that for the PPC405D5 CPU. Apparently,
FX12 device present
on the ML403 EVM incorporates another CPU, and that one most certainly
supports APU
FPU. I'd recommend to search Xilinx app notes page:
http://www.xilinx.com/support/documentation/virtex-4.htm#19333
for XAPP547.
HTH,
Andrew
< andrew dot nesterov at techemail dot com >
FreeRTOS.org
news:935ec02a-3602-4302...@d45g2000hsc.googlegroups.com...
> Hi Richard,
>
> The UG11's tbl 4-1 indicates that for the PPC405D5 CPU. Apparently,
> FX12 device present
> on the ML403 EVM incorporates another CPU, and that one most certainly
> supports APU
> FPU. I'd recommend to search Xilinx app notes page:
> http://www.xilinx.com/support/documentation/virtex-4.htm#19333
> for XAPP547.
Thanks for this link. I think the code it relates too I have actually
downloaded already - but for some reason I missed the accompanying .pdf.
The code project is for a previous version of the tools, and will not
upgrade correctly to the latest version, which was the problem with
progressing that route.
However, the document throws up an interesting things to try. It states
that installing the FPU should automatically change the compile time option
to generate FPU instructions - which my project has done - and also
automatically generate a couple of #defines - which it seems my project has
not done. This too could be because of a version mismatch, but it gives me
something to look at.
--
Regards,
Richard.
+ http://www.FreeRTOS.org & http://www.FreeRTOS.org/shop
17 official architecture ports, more than 5000 downloads per month.
FreeRTOS.org
>> FX12 device present
>> on the ML403 EVM incorporates another CPU, and that one most certainly
>> supports APU
>> FPU. I'd recommend to search Xilinx app notes page:
>> http://www.xilinx.com/support/documentation/virtex-4.htm#19333
>> for XAPP547.
>
>
> Thanks for this link. I think the code it relates too I have actually
> downloaded already - but for some reason I missed the accompanying .pdf.
> The code project is for a previous version of the tools, and will not
> upgrade correctly to the latest version, which was the problem with
> progressing that route.
>
> However, the document throws up an interesting things to try. It states
> that installing the FPU should automatically change the compile time
> option to generate FPU instructions - which my project has done - and also
> automatically generate a couple of #defines - which it seems my project
> has not done. This too could be because of a version mismatch, but it
> gives me something to look at.
Having got their reference project to compile/download, I find it jumps off
to lala land when the first flop instruction is executed :o(
Dmitriy Bekker
> Looking at the PPC405 block reference guide I am informed that I have to set
> bits 6 (APU present) and 18 (FCM floating point unit present) in the MSR
> register of the PPC405 in order for the APU to intercept the FPU
> instructions - but the PPC405 reference guide from Xilinx states that all
> these bits are unsupported and must be set to 0. This seems contradictory.
This should be set automatically when EDK compiles. No need to set
those bits. However, you do need to set the APU control configuration
register to 0b1 (right click on ppc405 core in EDK and go to APU tab).
> Any advice on how to add the APU FPU unit to a PPC405 design without FPU
> instructions generating exceptions would be gratefully received!
Other than that, just connect the FCB and FPU cores the same way as in
the application note (xapp547). If you want, you can look at my
Thesis, there is a lot of info on the Xilinx FPU:
http://hdl.handle.net/1850/4805
Good luck.
Dmitriy Bekker
> --
> Regards,
> Richard.
>
> +http://www.FreeRTOS.org
FreeRTOS.org
> This should be set automatically when EDK compiles. No need to set
> those bits. However, you do need to set the APU control configuration
> register to 0b1 (right click on ppc405 core in EDK and go to APU tab).
Hi,
Thanks for the info. It looks like the APU controller configuration
register initial value is set to 0b0000000000000001 already :o( I will
check out your thesis now.
--
Regards,
Richard.
+ http://www.FreeRTOS.org & http://www.FreeRTOS.org/shop
17 official architecture ports, more than 5000 downloads per month.