This issue was that there were some issues seen as USB EHCI port
failures under some conditions that have been reported on the mailing
list by a small percentage of users. We created a screen for the
issue (that currently takes a long time to run) and that slowed
production down for a while. Some help from the community in
improving the test case would help speed up production. I'll get back
with details on the current test case.
It is currently suspected that enabling re-tuning of the PLL at run-
time in the kernel might resolve the issue, but that code hasn't been
implemented yet and we don't want people to get stuck with boards that
have intermittent failures or fail under certain conditions. Help in
implementing that code would also be helpful. More details to follow
on that as well.