We're number 73
Del Cecchi
let me know and bring your visa card...
:-)
NEW YORK (AP) -- It's only the size of a dishwasher, but it's crammed with
1,024 microprocessors, housed in an innovative slanted cabinet and can
perform a whopping 2 trillion calculations per second, ranking it as one of
the world's fastest supercomputers. But this computing wonder, being shown
off Friday by IBM Corp., is only 1/128th of the finished product. When Blue
Gene/L, as the supercomputer is known, is delivered to Lawrence Livermore
National Laboratory just over a year from now, it will easily rank as the
world's fastest supercomputer. Its 130,000 processors will be able to
perform up to 360 trillion calculations per second, or 360 teraflops.
................
IBM revealed details of Blue Gene/L's design to coincide with the No. 73
ranking the initial segment achieved on Dongarra's latest list. IBM contends
that other machines of comparable power are 20 times bigger.
Among the breakthroughs: IBM used chips that combine several supercomputer
functions. Designers also slanted the machine's walls 11 degrees to speed
the entry of cool air and exit of hot air, slashing the supercomputer's need
for electricity-sucking air conditioning.
Thomas Womack
Del Cecchi <cec...@us.ibm.com> wrote:
>Here is the edited press release. If anyone wants one of their own, just
>let me know and bring your visa card...
How large a visa card do you need? Two teraflops peak is, umm, 350 or
so 3.2GHz Xeon machines, $1.3 million list price from IBM, but a lot
bigger han a dishwasher. How much cheaper than that is the Blue Gene
node? And how far does it break down -- is the idea to put a 32-CPU
slice of Blue Gene, for $20k, in every bioinformatics lab in the
country? Or a couple of CPUs, for $250, under every TV on the planet?
I'm not quite sure what proportion of peak is implied by being #73 on
today's Top500; #73 in 6/03 was 873G, 11/02 was 736G, 6/02 was 552G,
drop an exponential through them and you're not much more than 1100G,
<60% efficiency. But it's a waste of time extrapolating when the list
is out tomorrow.
Tom
Robert Myers
wrote:
>Here is the edited press release. If anyone wants one of their own, just
>let me know and bring your visa card...
>
>:-)
>
>
>NEW YORK (AP) -- It's only the size of a dishwasher, but it's crammed with
>1,024 microprocessors, housed in an innovative slanted cabinet and can
>perform a whopping 2 trillion calculations per second, ranking it as one of
>the world's fastest supercomputers. ...
<snip>
And here's the corresponding Reuters news lead:
http://www.forbes.com/home_asia/newswire/2003/11/14/rtr1147955.html
IBM builds supercomputer based on gaming chip
Reuters, 11.13.03, 11:59 PM ET
SAN FRANCISCO (Reuters) - International Business Machines Corp. said
Friday that it has built a supercomputer the size of a television
based on microchip technology to be used in gaming consoles due out
next year. ...
Maybe I'll just wait and buy a PS3. ;-).
RM
Wes Felter
> I'm not quite sure what proportion of peak is implied by being #73 on
> today's Top500; #73 in 6/03 was 873G, 11/02 was 736G, 6/02 was 552G,
> drop an exponential through them and you're not much more than 1100G,
> <60% efficiency. But it's a waste of time extrapolating when the list
> is out tomorrow.
The beta version of the list is at
http://www.netlib.org/benchmark/performance.pdf
Start on p.53. BlueGene/L is listed at 1.4TFLOPS or 70% of peak.
--
Wes Felter - wes...@felter.org - http://felter.org/wesley/
Del Cecchi
"Robert Myers" <rmy...@rustuck.com> wrote in message
news:ct5arv4cp9271l42t...@4ax.com...
>
>
Robert Myers
wrote:
<snip>
>I saw that. Maybe you best go read the press release. Sigh.
I actually made a diligent effort to find the underlying press release
that would make sense of the second lead or that would fill out the
details of the first, and I was unsuccessful in both cases.
The NY Times article makes much more sense, and says much more
interesting things than talking about either Top 500 rankings or game
chips:
"It will be air-cooled, as opposed to many high-performance machines
that use water and refrigeration, and it will use no more power than
the average home, the executives said. Computer scientists and
industry analysts said the Blue Gene/L represented a radical departure
from the industry's obsession with ever-faster microprocessor chips."
<snip>
"The prototype has 512 PowerPC 440 microprocessors, which are similar
to the I.B.M. 970 processor being used in Apple Computer's G5
Macintosh, but each with a lower clock speed. By lowering the clock
speed governing how fast the chip executes calculations, it is
possible to pack the processor chips far more closely together. Speed
is then made up in other areas of the computing system."
<snip>... "I.B.M. executives said they had been discussing the new
design widely in the computer industry, approaching large corporate
users of computing systems for commercial applications, like Internet
search engines."
More interesting than game chips or supercomputer rankings:
1. High-density design with lower clock speed for a supercomputer.
2. Low power consumption.
3. Architecture aimed at a larger market than chess championship demos
and one-off designs for national laboratories.
RM
del cecchi
> On Fri, 14 Nov 2003 15:31:36 -0600, "Del Cecchi" <cec...@us.ibm.com>
> wrote:
>
> <snip>
>
> >I saw that. Maybe you best go read the press release. Sigh.
>
> I actually made a diligent effort to find the underlying press release
> that would make sense of the second lead or that would fill out the
> details of the first, and I was unsuccessful in both cases.
>
> The NY Times article makes much more sense, and says much more
> interesting things than talking about either Top 500 rankings or game
> chips:
>
> "It will be air-cooled, as opposed to many high-performance machines
> that use water and refrigeration, and it will use no more power than
> the average home, the executives said. Computer scientists and
> industry analysts said the Blue Gene/L represented a radical departure
> from the industry's obsession with ever-faster microprocessor chips."
>
> <snip>
>
> "The prototype has 512 PowerPC 440 microprocessors, which are similar
> to the I.B.M. 970 processor being used in Apple Computer's G5
> Macintosh, but each with a lower clock speed. By lowering the clock
> speed governing how fast the chip executes calculations, it is
> possible to pack the processor chips far more closely together. Speed
> is then made up in other areas of the computing system."
The 440 PowerPC is, I believe, a core available from MicroElectronics
Division and is 32 bits. I guess it is similar for some definitions of
similar.
>
> <snip>... "I.B.M. executives said they had been discussing the new
> design widely in the computer industry, approaching large corporate
> users of computing systems for commercial applications, like Internet
> search engines."
I said just bring your Visa card. :-) you too could be the first one in
your office to have 1024 processors next to your desk. :-)
>
> More interesting than game chips or supercomputer rankings:
>
> 1. High-density design with lower clock speed for a supercomputer.
>
> 2. Low power consumption.
>
> 3. Architecture aimed at a larger market than chess championship demos
> and one-off designs for national laboratories.
>
> RM
del
>
>
Robert Myers
wrote:
<snip>
>
>The 440 PowerPC is, I believe, a core available from MicroElectronics
>Division and is 32 bits. I guess it is similar for some definitions of
>similar.
>
Info from the IBM website is a little sketchy, but there is a document
at llnl that is a little more forthcoming:
www.llnl.gov/asci/platforms/bluegenel/pdf/software.pdf
"The basic building block of Blue Gene/L is a custom system-on-a-chip
that integrates processors, memory and communications logic in the
same piece of silicon. The BG/L chip contains two standard 32-bit
embedded PowerPC 440 cores, each with private L1 32KB instruction and
32KB data caches. Each core also has a 2KB L2 cache and they share a
4MB L3 EDRAM cache. While the L1 caches are not coherent, the L2
caches are coherent and act as a prefetch buffer for the L3 cache.
Each core drives a custom 128-bit double FPU that can perform four
double precision floating-point operations per cycle. This custom FPU
consists of two conventional FPUs joined together, each having a
64-bit register file with 32 registers. One of the conventional
FPUs (the primary side) is compatible with the standard PowerPC
floating-point instruction set. We have extended the PPC instruction
set to perform SIMD-style floating point operations on the two FPUs.
In most scenarios, only one of the 440 cores is dedicated to run user
applications while the second processor drives the networks. At
a target speed of 700 MHz the peak performance of a node is 2.8
GFlop/s. When both cores and FPUs in a chip are used, the peak
performance per node is 5.6 GFlop/s. The standard PowerPC 440 cores
are not designed to support multiprocessor architectures:
the L1 caches are not coherent and the architecture lacks atomic
memory operations. To overcome these limitations BG/L provides a
variety of synchronization devices in the chip: lockbox, shared SRAM,
L3 scratchpad and the blind device. The lockbox unit contains a
limited number of memory locations for fast atomic test-and-sets
and barriers. 16 KB of SRAM in the chip can be used to exchange data
between the cores and regions of the EDRAM L3 cache can be reserved as
an addressable scratch-pad. The blind device permits explicit cache
management."
The map to Red Storm that suggests itself is unmistakeable: one
processor, one networking element per compute node. The other
interesting feature is the four-wide double precision FP unit (if the
second processor is not in use for networking). Now we are up to an
SIMD vector length of 4 for double precision floating point. It's
also worth noting that the 700 MHz target speed is significantly above
the 550 MHz in the specification document on the IBM web site. Nice
to see that IBM is into overclocking.
RM
Niels Jørgen Kruse
<rmy...@rustuck.com> skrev:
> The map to Red Storm that suggests itself is unmistakeable: one
> processor, one networking element per compute node. The other
> interesting feature is the four-wide double precision FP unit (if the
> second processor is not in use for networking). Now we are up to an
> SIMD vector length of 4 for double precision floating point. It's
> also worth noting that the 700 MHz target speed is significantly above
> the 550 MHz in the specification document on the IBM web site. Nice
> to see that IBM is into overclocking.
From 2 TFLOPS peak with 1024 cores, and 4 FLOP/clock, we get ~500 MHz. No
overclocking there. The target speed is likely for a 90 nm process.
--
Mvh./Regards, Niels Jørgen Kruse, Vanløse, Denmark
Michael S
Del,
Would you be so kind to explain how 2-way superscalar core like 440
can keep dual FPU busy? The only way I can think of is SIMD.
del cecchi
"Michael S" <already...@yahoo.com> wrote in message
news:f881b862.03111...@posting.google.com...
I'm sorry but there are two reasons I can't supply the desired
explanation. First is that I don't know the answer although I probably
could find out. Second is that I don't know that information has been
made public and I am pretty careful not to divulge otherwise private
information. Gotta eat and all that. Maybe someone else will be able
to comment.
del cecchi
Niels Jørgen Kruse
already...@yahoo.com (Michael S) skrev:
> Would you be so kind to explain how 2-way superscalar core like 440
> can keep dual FPU busy? The only way I can think of is SIMD.
Robert Myers posted a quote from a LLNL paper. Perhaps Google missed it?
People have complained (in other groups) about posts not showing up in
Google.
The relevant part of the quote is:
> Each core drives a custom 128-bit double FPU that can perform four
> double precision floating-point operations per cycle. This custom FPU
> consists of two conventional FPUs joined together, each having a
> 64-bit register file with 32 registers. One of the conventional
> FPUs (the primary side) is compatible with the standard PowerPC
> floating-point instruction set. We have extended the PPC instruction
> set to perform SIMD-style floating point operations on the two FPUs.
--
Michael S
> I artiklen <f881b862.03111...@posting.google.com> ,
> already...@yahoo.com (Michael S) skrev:
>
> > Would you be so kind to explain how 2-way superscalar core like 440
> > can keep dual FPU busy? The only way I can think of is SIMD.
>
> Robert Myers posted a quote from a LLNL paper. Perhaps Google missed it?
> People have complained (in other groups) about posts not showing up in
> Google.
>
I saw Robert's post shortly after posting my question. I don't know
whom to blame, Google or myself :-)
Mike Cormack
"Del Cecchi" <cec...@us.ibm.com> wrote in message
news:bp2s7u$k3m$1...@news.rchland.ibm.com...
del cecchi
"Mike Cormack" <mike.c...@intel.com> wrote in message
news:bpba5p$ojb$1...@news01.intel.com...
> Does it use Infinibad technology?
No.
>
> "Del Cecchi" <cec...@us.ibm.com> wrote in message
> news:bp2s7u$k3m$1...@news.rchland.ibm.com...
> > Here is the edited press release. If anyone wants one of their own,
just
> > let me know and bring your visa card...
> >
snip