Static Timing Analysis

Project : eeprom_v100
Build Time : 02/14/17 10:29:53
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 60.205 MHz
UART_1_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 57.527 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 60.205 MHz 16.610 25.057
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 4.934
macrocell6 U(1,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(1,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 86.866 MHz 11.512 30.155
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.993
macrocell18 U(1,1) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 86.866 MHz 11.512 30.155
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.993
macrocell23 U(1,1) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 87.002 MHz 11.494 30.173
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.975
macrocell15 U(1,1) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 87.017 MHz 11.492 30.175
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.973
macrocell24 U(0,1) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 95.666 MHz 10.453 31.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 4.934
macrocell21 U(1,0) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 95.666 MHz 10.453 31.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 4.934
macrocell22 U(1,0) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 57.527 MHz 17.383 1065.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 4.352
macrocell2 U(0,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.241
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 58.018 MHz 17.236 1066.097
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 4.205
macrocell2 U(0,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.241
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 61.271 MHz 16.321 1067.012
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,1) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 4.048
macrocell5 U(1,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.313
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 62.383 MHz 16.030 1067.303
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 2.999
macrocell2 U(0,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.241
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 62.850 MHz 15.911 1067.422
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,1) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 3.638
macrocell5 U(1,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.313
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 64.325 MHz 15.546 1067.787
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,1) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 3.273
macrocell5 U(1,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.313
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 67.195 MHz 14.882 1068.451
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,1) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 2.609
macrocell5 U(1,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.313
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 67.522 MHz 14.810 1068.523
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 2.839
macrocell2 U(0,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.241
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 75.988 MHz 13.160 1070.173
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,0) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 2.243
macrocell6 U(1,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(1,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 76.046 MHz 13.150 1070.183
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,0) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_postpoll\/main_2 2.233
macrocell6 U(1,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(1,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.943
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 4.934
macrocell21 U(1,0) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.943
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 4.934
macrocell22 U(1,0) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 7.982
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.973
macrocell24 U(0,1) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 7.984
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.975
macrocell15 U(1,1) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 8.002
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.993
macrocell18 U(1,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 8.002
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.993
macrocell23 U(1,1) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 13.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 4.934
macrocell6 U(1,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(1,1) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 1.559
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(1,1) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.309
statusicell2 U(0,1) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.956
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART_1:BUART:rx_count_0\ \UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.336
macrocell19 U(0,1) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_2\/main_2 3.029
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_2\/main_2 2.839
macrocell12 U(0,0) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_bitclk\/main_2 3.029
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_bitclk\/main_2 2.839
macrocell13 U(0,0) 1 \UART_1:BUART:tx_bitclk\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 3.179
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 2.989
datapathcell1 U(1,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_1\/main_2 3.197
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_1\/main_2 3.007
macrocell10 U(1,0) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 3.197
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 3.007
macrocell11 U(1,0) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 3.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 2.630
macrocell16 U(1,1) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_2\/main_7 3.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_2\/main_7 2.630
macrocell18 U(1,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_0\/main_7 3.261
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_0\/main_7 2.641
macrocell15 U(1,1) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 31.284
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_2/main_0 3.126
macrocell1 U(0,1) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q Tx_1(0)/pin_input 6.591
iocell2 P12[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.967
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000