Static Timing Analysis

Project : CapSense_CSD_P4_Example_WithTuner01
Build Time : 05/25/16 20:20:56
Device : CY8C4126LTQ-M445
Temperature : -40C - 85C
VDDA_0 : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDD_0 : 3.30
VDDD_1 : 3.30
VDDIO : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDIO_A : 3.30
VDDIO_A_1 : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CapSense_CSD_SampleClk(FFB) CapSense_CSD_SampleClk(FFB) 94.118 kHz 94.118 kHz N/A
CapSense_CSD_SenseClk(FFB) CapSense_CSD_SenseClk(FFB) 94.118 kHz 94.118 kHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
CapSense_CSD_SampleClk CyHFCLK 94.118 kHz 94.118 kHz N/A
CapSense_CSD_SenseClk CyHFCLK 94.118 kHz 94.118 kHz N/A
SCB_SCBCLK CyHFCLK 8.000 MHz 8.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
SCB_SCBCLK(FFB) SCB_SCBCLK(FFB) 8.000 MHz 8.000 MHz N/A