PCB Layout Designers
Tom
Guess this is really 2 questions, first up.....
I am still using an old DOS version of EasyPC Pro for PCB layout,
mainly because they want a stack load of money to upgrade. I did a
long time ago post a question about free PCB packages, and found one,
but the problem was that the package really relies on entering the
schematic first, creating the nets the polishing the layout afterwards
in PCB mode.
I don't actually dot he circuit designs, the company is my fathers, he
designs them, I translate his PCB designs on paper to designs in
EasyPC for printing out and either home manufacture or for sending of
for bulk manufacture.
Does anyone know of an existing package that allows for this approach,
ie not bothering with the schematic?
The second question....
This is kind of related to the first, I'd be interested to know if
everyone designs their PCB's from the schematic stage upwards on
computers, or whether there are many people creating the PCB layout
only?
Tom
OBones
just because the PCB tool verifies that I did not leave any connection
unrouted. And with more than 20 nets, this becomes increasingly
interesting to have.
Paul Burke
I am still using an old DOS version of EasyPC Pro for PCB layout,
> mainly because they want a stack load of money to upgrade.
I don't think £447 is excessive for the features you get with the
complete unlimited version. And by the sound of it, your PCBs could
almost certainly get away with one of the limited versions.
> Does anyone know of an existing package that allows for this approach,
> ie not bothering with the schematic?
>
You can enter directly to the PCB with EasyPC (always have been able to
as far as I know), and add the nets manually. Recent versions will
produce a ratnested schematic from the laid out PCB.
> This is kind of related to the first, I'd be interested to know if
> everyone designs their PCB's from the schematic stage upwards on
> computers, or whether there are many people creating the PCB layout
> only?
For anything except trivial PCBs (a resistor and a LED say), it's always
more secure to start with the schematic. It's much easier to verify. But
also remember to verify the PCB packages. Never trust your own library,
let alone someone else's.
Paul Burke
David L. Jones
Protel AutoTrax will do exactly what you want, it's now freeware.
http://www.altium.com/Community/Support/Downloads/
A lot of people (Hobbyists and one-man-bands mostly) still do the PCB
only from a handdrawn schematic, but almost no one does that in
professional circles.
AutoTrax will even let you generate a netlist from your hand drawn
PCB, and then you can still do some basic DRC checking.
Dave.
Robert Latest
> Does anyone know of an existing package that allows for this approach,
> ie not bothering with the schematic?
Sure, EAGLE from CadSoft. It comes in three modules -- schematic, board
editor, and autorouter -- that you can buy seperately. So if you only buy
the board editor you get exactly the functionality you want.
> This is kind of related to the first, I'd be interested to know if
> everyone designs their PCB's from the schematic stage upwards on
> computers, or whether there are many people creating the PCB layout
> only?
Everybody (except your dad) does it in CAD, from schematic upwards. It's
sooo much easier to maintain consistency between schematic and board. Of
course many people first draw schematics by hand, but before they go to the
board stage they'll recreate the schematic in CAD and then do the board in
CAD as well.
Remember: If the CAD schematic is correct, there is NO WAY the corresponding
board could be electrically faulty (i.e., have missing or wrong connections
between parts) because the CAD package will always ensure 100% consistency.
Or is anybody aware of a CAD system that doesn't maintain board-schematic
consistency? That would be something to steer clear of.
robert
Paul Burke
>
> Remember: If the CAD schematic is correct, there is NO WAY the corresponding
> board could be electrically faulty
Well most programs have the odd bug now and again. But it does reduce
the incidence.
DJ Delorie
gEDA's PCB was originally designed to work standalone, and it still
retains that capability. You can pull component footprints from the
parts library, connect up pins to form a ratlist, then route it. It
can even use a scan of a pre-existing board as the background, to act
as a template for replicating lost designs.
Spehro Pefhany
<bobl...@yahoo.com> wrote:
It's correct, almost by definition, but there are ways a schematic can
*look* correct, and not be. That's why (in addition to running DRC, of
course) I always create a human-readable netlist and give it a decent
lookover (thanks to, IIRC, John L for this suggestion).
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
sp...@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Robert Baer
require the schematic, and if you *do* use it, the result is a bit
clunky - slightly better than a kick in the head (unless there most
recent update improved matters).
BUT, the result is that you have them do the boards, typically in
pairs (2, 4, 6, etc).
If you want gerbers from their software, forget it.
I have made pc boards since the early 1970s and always have done them
"by hand" (first black tape, then blue/red/black, and now via software).
Robert Baer
Is it still the case that gEDA will not work in WinDoze?
Rene Tschaggelar
AutoCAD ? A few footprints and you're there.
Rene
DJ Delorie
Robert Baer <rober...@earthlink.net> writes:
> Is it still the case that gEDA will not work in WinDoze?
gEDA has worked in Windows for a while now.
We just don't have a pre-built binary for it. But then again, we
don't have pre-built binaries for Linux either. So, you have to
figure out how to build and install it yourself. PCB at least comes
with suitable scripts and readme's for building under Windows.
Tom
Sorry, I was not very clear there, yes EasyPC does indeed allow this
and always has, and although £447 is not that much, for a one man band
that only uses it occasionally if there were a cheaper or freeware
version around that oly provided the libraries/gerber/drill and PCB
design function that would be preferable.
The designs in question are considerably more complicated than a
resistor and LED ;-) However a lot of complexity is removed by the
user of PIC's, and all of them have been made in production releases
on vero-board before the PCB exists, so the design is is well known by
my father.
The final fly in the ointment is that my father is not a computer
competent person.
Tom
Robert Baer
Maybe for you, but nothing ever works for me the first, second or
third time.
And in this case, one would have to somehow get the compilers (wil be
more than one with my luck).
Worse, the smallest download will be over 4megs, making it impossible
(i am on dial-up).
So, for gEDA, i would need a pre-built binary on CD.
Net result? gEDA will not work for me.
Tom
> On May 22, 4:32 pm, Tom <t...@ts-net.co.uk> wrote:
>
>
>
>
>
> > Morning All
>
> > Guess this is really 2 questions, first up.....
>
> > I am still using an old DOS version of EasyPC Pro for PCB layout,
> > mainly because they want a stack load of money to upgrade. I did a
> > long time ago post a question about free PCB packages, and found one,
> > but the problem was that the package really relies on entering the
> > schematic first, creating the nets the polishing the layout afterwards
> > in PCB mode.
>
> > I don't actually dot he circuit designs, the company is my fathers, he
> > designs them, I translate his PCB designs on paper to designs in
> > EasyPC for printing out and either home manufacture or for sending of
> > for bulk manufacture.
>
> > Does anyone know of an existing package that allows for this approach,
> > ie not bothering with the schematic?
>
> > The second question....
>
> > This is kind of related to the first, I'd be interested to know if
> > everyone designs their PCB's from the schematic stage upwards on
> > computers, or whether there are many people creating the PCB layout
> > only?
>
> > Tom
>
>
> A lot of people (Hobbyists and one-man-bands mostly) still do the PCB
> only from a handdrawn schematic, but almost no one does that in
> professional circles.
>
> AutoTrax will even let you generate a netlist from your hand drawn
> PCB, and then you can still do some basic DRC checking.
>
>
> - Show quoted text -
Yep, the old boy is exactly that, the one man band!
I was really looking for something was Windows and current rather than
DOS. Easy PC does the job, but the version we have is an old DOS
program and the libraries are rather old now.
Tom
Tom
Hmm, this one really raised my hopes, what I failed to indicate was a
Windows requirement.
Tom
qrk
wrote:
>Remember: If the CAD schematic is correct, there is NO WAY the corresponding
>board could be electrically faulty
I've seen Orcad Layout v10.x, on multiple occasions, mung up the net
list mid way thru the project. It would tie separate nets together. At
the end of the project, I reimport the netlist just in case Layout did
something evil.
---
Mark
Mike Monett
> It's correct, almost by definition, but there are ways a schematic can
> *look* correct, and not be. That's why (in addition to running DRC, of
> course) I always create a human-readable netlist and give it a decent
> lookover (thanks to, IIRC, John L for this suggestion).
> Best regards,
> Spehro Pefhany
What kind of errors are you looking for? It sounds like a lot of work, and
it won't catch mistakes such as typos on part values.
Maybe it would be better to fix the conditions that lead to the errors in
the first place.
For example, .1uf is sometimes hard to read when the decimal is obscured,
so people usually put a zero in front to clarify: 0.1uf. Others may use "R"
in place of the decimal, such as 1R5 for a 1.5k resistor.
I'm sure there are many other ways of doing schematics that help avoid
mistakes, and developing these good habits can save a lot of time and
grief. If you can only find 90% of the mistakes, it pays to reduce the
number in the first place.
I tend to pick up most things in pcb layout and routing, so for me, a cad
package that does back annotation is essential. I found trying to do it
manually is very error-prone:)
Regards,
Mike Monett
Spehro Pefhany
<N...@email.adr> wrote:
>Spehro Pefhany <spef...@interlogDOTyou.knowwhat> wrote:
>
>> It's correct, almost by definition, but there are ways a schematic can
>> *look* correct, and not be. That's why (in addition to running DRC, of
>> course) I always create a human-readable netlist and give it a decent
>> lookover (thanks to, IIRC, John L for this suggestion).
>
>> Best regards,
>> Spehro Pefhany
>
>What kind of errors are you looking for? It sounds like a lot of work, and
>it won't catch mistakes such as typos on part values.
Mostly stuff like hidden connections to supplies that have a variety
of different names. For example, Vss, GND, Vee, etc. which can form an
isolated net if there are multiple parts that use the same name, but
you forget to check the names on every part with hidden power pins and
make sure it's tied to the proper supply. That would normally get
caught at layout, but it's better to catch it earlier. Similarly,
typos on labels could lead to isolated nets with more than one node,
so that DRC isn't likely going to catch it.
>Maybe it would be better to fix the conditions that lead to the errors in
>the first place.
>
>For example, .1uf is sometimes hard to read when the decimal is obscured,
>so people usually put a zero in front to clarify: 0.1uf. Others may use "R"
>in place of the decimal, such as 1R5 for a 1.5k resistor.
>
>I'm sure there are many other ways of doing schematics that help avoid
>mistakes, and developing these good habits can save a lot of time and
>grief. If you can only find 90% of the mistakes, it pays to reduce the
>number in the first place.
I prefer to show all the power pins on parts, but sometimes that makes
the schematic too messy, and that could obscure other problems.
>I tend to pick up most things in pcb layout and routing, so for me, a cad
>package that does back annotation is essential. I found trying to do it
>manually is very error-prone:)
>
>Regards,
>
>Mike Monett
A number of years ago I was converting a schematic from hand-drawn to
electronic and was a bit surprised to notice an obvious error. I'd
fixed it without even noticing in the (manual) layout. Unfortunately,
computers don't "know what you meant" to draw.
Mike Monett
> On Tue, 22 May 2007 18:27:00 +0000, the renowned Mike Monett
> <N...@email.adr> wrote:
>> What kind of errors are you looking for? It sounds like a lot of
>> work, and it won't catch mistakes such as typos on part values.
> Mostly stuff like hidden connections to supplies that have a
> variety of different names. For example, Vss, GND, Vee, etc. which
> can form an isolated net if there are multiple parts that use the
> same name, but you forget to check the names on every part with
> hidden power pins and make sure it's tied to the proper supply.
> That would normally get caught at layout, but it's better to catch
> it earlier. Similarly, typos on labels could lead to isolated nets
> with more than one node, so that DRC isn't likely going to catch
> it.
Like you, I prefer to show all the nets on the schematic so they
light up when you select them. Hidden nets are a recipe for
disaster.
I usually end up writing a separate program to assist in naming
nets, entering proper component values, generating the pin
connections on new packages, and anything else that is tedious and
error-prone. Most cad packages have macro capability which makes it
easy to enter the data, or you can simply paste it into a data entry
box.
Anything that reduces the chance for human error is worth
considering, no matter how small or trivial it may seem.
A mistake takes only a second. Finding it can take weeks:)
[...]
> I prefer to show all the power pins on parts, but sometimes that
> makes the schematic too messy, and that could obscure other
> problems.
I think the schematic should show everything - unused pins, unused
sections of ics, power supply filtering, all bypass caps
(naturally), and anything else that helps understand each connection
on the board. I usually add separate pages at the end to show all
this stuff.
[...]
> A number of years ago I was converting a schematic from hand-drawn
> to electronic and was a bit surprised to notice an obvious error.
> I'd fixed it without even noticing in the (manual) layout.
> Unfortunately, computers don't "know what you meant" to draw.
Soon, maybe. As mentioned above, I try to add as much as possible in
a separate data entry program and get it to check the info before
putting it into the schematic. That saves a lot of time and greatly
reduces the number of errors.
> Best regards,
> Spehro Pefhany
Regards,
Mike Monett
jo...@jjdesigns.fsnet.co.uk
> Morning All
[...]
> The second question....
>
> This is kind of related to the first, I'd be interested to know if
> everyone designs their PCB's from the schematic stage upwards on
> computers, or whether there are many people creating the PCB layout
> only?
>
> Tom
I've come across a number of commercial designers that still route
manually. They'll go the circuit diagram route only if the board
complexity demands it (say 20 or more packages). They say the main
reason is time saving from not having to fart about creating unique
library components and the ensuing struggle with third rate diagram
editors.
JeffM
>>gEDA's PCB was originally designed to work standalone,
>>It can even use a scan of a pre-existing board as the background,
>>to act as a template for replicating lost designs.
>>
>Hmm, this one really raised my hopes,
>what I failed to indicate was a Windows requirement.
"Installing gEDA/gaf on Windows--the Cygwin way" by werner
http://www.google.com/search?q=cache:kMEQLrxfhx8J:www.geda.seul.org/wiki/geda:cygwin+the.Cygwin.way+gschem.and.friends+Installing.gEDA+zz+zz+qq+on-Windows
You can test drive gEDA without installing it (even on a Windoze box):
http://groups.google.com/group/sci.electronics.cad/browse_frm/thread/3b6f24029a8b34cf/5ef0c2c6f82294d6?q=*-Knoppix-like-CD-with-gEDA-*-*+Quantian+Cygwin+Win-2000-or-XP+Gtk.libraries+MinGW+qq+*-distro-*-*-providing-open-source-scientific-and-engineering-apps+recent.improvements
DJ Delorie
For just pcb, Dan has a windows installer I've pre-tested. It's
mingw-based, no cygwin required.
rebel
snip)
>For example, .1uf is sometimes hard to read when the decimal is obscured,
>so people usually put a zero in front to clarify: 0.1uf. Others may use "R"
>in place of the decimal, such as 1R5 for a 1.5k resistor.
Crikey, 1R5 is a looong way from 1.5k. I hope* that was just a typo or brain
fade there Mike.
budgie
>I've come across a number of commercial designers that still route
>manually. They'll go the circuit diagram route only if the board
>complexity demands it (say 20 or more packages). They say the main
>reason is time saving from not having to fart about creating unique
>library components and the ensuing struggle with third rate diagram
>editors.
I'm a one-man band when it comes to circuit and pcb design, and I prefer manual
layout (two layers only) over importing a schematic into the pcb software. I
find that:
. package placement is easier without the ratsnest, but with the ability to
have just a selection of interconnections showing.
. the autorouter is great at achieving 85% faster than me, but often fails to
complete and I have to undo sooo much that I haven't used autorouting in the
last five years.
. I have developed a fairly thorough and successful checking process that
hasn't let a layout/connection error through in those five years.
rebel
>Protel AutoTrax will do exactly what you want, it's now freeware.
>http://www.altium.com/Community/Support/Downloads/
Now all they need to do is formally release Schematic into the public domain.
Mike Monett
Brain fade. Focus on one thing, and type something else.
Of course, my data entry software would have caught that instantly. It
knows I don't normally use 1.5 ohm resistors!
That's where writing your own cad interface can really help. It checks the
value to ensure it is legal, checks stock to see if it needs to be ordered,
and checks the part history to see if the component is common or seldom
used. If there is any problem, it shows a message with the infomation and
asks if you really want to do that. Binary searches are used wherever
possible so the results are instantaneous and it doesn't slow you down.
Checks like these can do a lot to ensure the data is correct before it is
entered into the cad program. The whole idea is to let the computer take
care of the details, and to keep bad or erroneous data from entering the
system in the first place.
Regards,
Mike Monett
Robert Latest
> It's correct, almost by definition, but there are ways a schematic can
> *look* correct, and not be. That's why (in addition to running DRC, of
> course) I always create a human-readable netlist and give it a decent
> lookover (thanks to, IIRC, John L for this suggestion).
Absolutely. I started doing this after I had accidentally stumbled across
mistakes in a netlist that I had created for a different purpose.
robert
Robert Latest
> On 22 May 2007 09:52:59 GMT, Robert Latest <bobl...@yahoo.com>
> wrote:
>
>>Remember: If the CAD schematic is correct, there is NO WAY the corresponding
>>board could be electrically faulty
>
> I've seen Orcad Layout v10.x, on multiple occasions, mung up the net
> list mid way thru the project. It would tie separate nets together.
I'd consider that a serious bug, and I don't consider a program that has
this bug to be an electronics CAD package. I mean, this routine stuff is the
FIRST THING that such CAD programs MUST DO RIGHT 100%.
robert
Paul Burke
>
>
> . package placement is easier without the ratsnest, but with the ability to
> have just a selection of interconnections showing.
I find the ratsnest very useful, particularly used in conjunction with
connection swap and back- annotation to the schematic. But then, I'm
usually tracking microcontroller and/or PLD designs for logic. It lets
you optimise positions and pinouts for easy routing before a trace is laid.
> . the autorouter is great at achieving 85% faster than me, but often fails to
> complete and I have to undo sooo much that I haven't used autorouting in the
> last five years.
That's not unusual. All but the most expensive autorouters need lots of
spare PCB.
Paul Burke
John Larkin
We recently did a board that has over 1000 parts, including a uP and
two FPGAs, 8 layers, parts on both sides. Hand checking that would
probably take two people a week or so, one calling out connections and
the other tracing them. PADS will do a full connectivity check on this
board in about 2 seconds, and a full design-rule check in under 10.
We do the full schematic thing for even the tiniest boards. One nice
thing is that you can ECO a schematic and export the changes to the
PCB and keep things in sync. You can also resequence the ref
designators on the board and back-annotate the schematic. We formally
release the schematic and the PCB files together, and we have a rule
that they *must* fully cross-check.
We never autoroute, and almost always go with the pins as originally
assigned on the schematic, ie no pin or gate swapping. We also often
pass the design around from person to person. An engineer may do some
critical placement as a model, our layout guy does the real work, then
another engineer or two may have a final lick at it, checking critical
clock nets and such.
John
qrk
wrote:
I do too. However, since Orcad moved their developement to India,
there are many bugs they have introduced, some scarry, some annoying.
---
Mark
D from BC
I treat my autorouter like a dog on a chain...
(What's smarter ...An autorouter or a dog? )
The dog can pull on the chain in all different directions.
I use a short chain and never let the dog loose..
Training helps...
I've had better results by tweeking the autorouting settings.
So... I just beat my autorouter with a rolled up newspaper when it's
bad.
(I wouldn't do that to a dog..just the autorouter..)
I take my autorouter for short walks only..always on the chain..When I
don't like where the dog is going..I just pull on the chain..
Some autorouter users I can imagine just let all the untrained dogs
out and the pcb turns into a mess..
Right...like they think they got the Hal 9000 doing the routing.. :)
D from BC
qrk
Some systems, you can turn off the rats nest. I usually do this when
placing parts.
Don't know why you want to suffer thru hand checking a board! DRC
takes less than a minute on most of my boards. I remember the days of
two people hand checking a board for 4 to 8 hours. Hate to think how
much time my last board with 1800 parts would take to hand check the
connectivity.
---
Mark
Joel Kolstad
news:v01953pbjjde1db2s...@4ax.com...
> We do the full schematic thing for even the tiniest boards.
I've probably asked before, but what did you say your schematic capture tool
of choice is?
> We never autoroute, and almost always go with the pins as originally
> assigned on the schematic, ie no pin or gate swapping.
Is that because... you're thinking the particular pin or gate used might have
been done so for a reason?
In general I find pin and gate swapping of great help, and the guy who entered
the schematic can just set the appropriate attribute if he doesn't want the
pin or gate swapping enabled for the net in question.
We use ORCAD and PADS for production PCBs, but have no path to back-annotate
reference designator changes in PADS back to the schematic (other than doing
it manually, of course). We've occasionally looked around at third-party
tools such as Prescience to do this, but no one ever had enough time to do a
serious eval.
---Joel
John Larkin
<JKolstad7...@yahoo.com> wrote:
>"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> wrote in message
>news:v01953pbjjde1db2s...@4ax.com...
>> We do the full schematic thing for even the tiniest boards.
>
>I've probably asked before, but what did you say your schematic capture tool
>of choice is?
We use PADS-Logic for schematic entry and PADS PowerPCB v5 for layout.
Bugs/crashes are virtually nonexistant. Logic the nicest schematic
editor I've ever used.
>
>> We never autoroute, and almost always go with the pins as originally
>> assigned on the schematic, ie no pin or gate swapping.
>
>Is that because... you're thinking the particular pin or gate used might have
>been done so for a reason?
Not really. If we expect congestion (say, a dozen 12-bit ADCs feeding
a big FPGA) we pre-plan the connections before we enter the schematic,
so things flow pretty well. For smaller glue-logic type stuff, our
layout guy seems to just make it work.
In a few recent cases, we told our guy to just use any one of a bunch
of uncommitted FPGA pins, whichever way worked easiest, and let him
handle it. I guess he did hot-wire the connections on the board and
back-annotate the schematic, which is technically not pin-swapping
because there never were any pins to swap! We can finally export the
board netlist and use that to make the FPGA pin constraints file.
>
>In general I find pin and gate swapping of great help, and the guy who entered
>the schematic can just set the appropriate attribute if he doesn't want the
>pin or gate swapping enabled for the net in question.
>
>We use ORCAD and PADS for production PCBs, but have no path to back-annotate
>reference designator changes in PADS back to the schematic (other than doing
>it manually, of course).
PADS just does that. When you resequence, it makes a back-ECO file. If
you use Orcad for schematics and PADS for layout, maybe that won't
work.
PADS does, or can do, anything in ASCII. You can export an entire
design in readable ascii form, pcb or schematic, and even include the
library symbols if you like. That lets us look at and process the
files if we want, which is sometimes handy. We've had one or two cases
of weird behavior that were fixed by an ascii export-import cycle.
John
John Larkin
>Don't know why you want to suffer thru hand checking a board! DRC
>takes less than a minute on most of my boards. I remember the days of
>two people hand checking a board for 4 to 8 hours. Hate to think how
>much time my last board with 1800 parts would take to hand check the
>connectivity.
Yeah, that was tedious. A half-dozen "verify connectivity" runs, using
maybe a minute total of CPU time, essentially pays for the entire pcb
cad suite!
John
David L. Jones
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Wed, 23 May 2007 09:23:55 +0800, budgie <m...@privacy.net> wrote:
We go a few steps better with Altium Designer and make sure every part
in our library has the full datasheet attached to every component,
along with a physical 3D model, and all the required manufacturing and
sourcing details. It's a lot of work up front, but it really pays
dividends when you can simply hit a button and generate full
manufacturing and purchasing BOM's and *know* it's all correct.
Datasheet linking is like having a scrolly-wheel mouse, once you've
used it you never want to go back.
Dave.
David L. Jones
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
We go a few steps better with Altium Designer and make sure every part
budgie
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Wed, 23 May 2007 09:23:55 +0800, budgie <m...@privacy.net> wrote:
>
>>I'm a one-man band when it comes to circuit and pcb design, and I prefer manual
>>layout (two layers only) over importing a schematic into the pcb software. I
>>find that:
>>
>>. package placement is easier without the ratsnest, but with the ability to
>>have just a selection of interconnections showing.
>>. the autorouter is great at achieving 85% faster than me, but often fails to
>>complete and I have to undo sooo much that I haven't used autorouting in the
>>last five years.
>>. I have developed a fairly thorough and successful checking process that
>>hasn't let a layout/connection error through in those five years.
>
>We recently did a board that has over 1000 parts, including a uP and
>two FPGAs, 8 layers, parts on both sides. Hand checking that would
>probably take two people a week or so, one calling out connections and
>the other tracing them. PADS will do a full connectivity check on this
>board in about 2 seconds, and a full design-rule check in under 10.
We operate in different worlds, John { ;) >
(snip)
>We never autoroute
I wonder how many do autoroute at both your level and down here at the base
where I operate. The tools are there, but I don't think it is ego that stops
most layout people lwetting the autorouter have a go.
> and almost always go with the pins as originally
>assigned on the schematic, ie no pin or gate swapping. We also often
>pass the design around from person to person. An engineer may do some
>critical placement as a model, our layout guy does the real work, then
>another engineer or two may have a final lick at it, checking critical
>clock nets and such.
I'm surprised that you don't accommodate gate swapping. Assigning a gate from a
package at schematic time is an arbitrary thing, and can't second-guess which
gate will provide the best layout.
budgie
>On Wed, 23 May 2007 09:23:55 +0800, budgie <m...@privacy.net> wrote:
>
>>I'm a one-man band when it comes to circuit and pcb design, and I prefer manual
>>layout (two layers only) over importing a schematic into the pcb software. I
>>find that:
>>
>>. package placement is easier without the ratsnest, but with the ability to
>>have just a selection of interconnections showing.
>>. the autorouter is great at achieving 85% faster than me, but often fails to
>>complete and I have to undo sooo much that I haven't used autorouting in the
>>last five years.
>>. I have developed a fairly thorough and successful checking process that
>>hasn't let a layout/connection error through in those five years.
>
>Some systems, you can turn off the rats nest. I usually do this when
>placing parts.
So did I (turn off ratsnest) when I tried the autorouting approach, but it would
be nice to be able to selectively turn off groups of connections so that only
strategic ones were left on. For example (see my reply to JL) gate-swapping -
package placement vs gate selection could be experimented with. I avoid the
term "optimised", as gate selection driving placement can easily compromise
other design aspects/criteria.
>Don't know why you want to suffer thru hand checking a board! DRC
>takes less than a minute on most of my boards. I remember the days of
>two people hand checking a board for 4 to 8 hours. Hate to think how
>much time my last board with 1800 parts would take to hand check the
>connectivity.
I operate in a different end of the field, 100 components is more typical.
Spehro Pefhany
<alt...@gmail.com> wrote:
How do you handle data sheet revisions? Some, particularly
semiconductors, tend to have a number during the life of the part. Do
you attach multiple datasheets if there are multiple vendors?
David L. Jones
In many cases you just *have* to autoroute some parts of a board. On
very complex and dense boards with hundreds or thousands of I/O it can
be simply too time consuming to route manually, especially the non-
critical traces. And with todays shrinking design cycle times, you
can't waste time with lots of manual routing.
Autorouting can be an essential and very powerful tool in the hands of
someone who knows how to use it selectively.
Dave.
David L. Jones
David L. Jones
<speffS...@interlogDOTyou.knowwhat> wrote:
We generally overwrite the linked datasheet with the latest revision.
However if there is a reason to keep multiple datasheets then we can
add as many linked documents to a part as we want, labeled
appropriately (datasheet-Rev1.pdf etc ). This includes app notes too.
>Do you attach multiple datasheets if there are multiple vendors?
Yes, we do that, and we can also have a selection of footprints for
the same device and have it associated with a different ordered part.
It's fantastic having a built up library of components all with linked
datasheets, app notes, multiple footprints, purchasing info etc, makes
future designs real easy. What's more, basic parametric info is also
included with each part, so you can often select a suitable device
from the library without even having to view the linked datasheet, and
you can sort lists of components by any parameter to make it even
easier.
Dave.
John Larkin
Autorouters don't have strategies, like people can, so start at a huge
disadvantage. They often make such a mess of a board that it takes
more time to clean it up than it would have taken to do it manually.
Not to mention the unbearable ugliness most autorouters create.
>
>> and almost always go with the pins as originally
>>assigned on the schematic, ie no pin or gate swapping. We also often
>>pass the design around from person to person. An engineer may do some
>>critical placement as a model, our layout guy does the real work, then
>>another engineer or two may have a final lick at it, checking critical
>>clock nets and such.
>
>I'm surprised that you don't accommodate gate swapping. Assigning a gate from a
>package at schematic time is an arbitrary thing, and can't second-guess which
>gate will provide the best layout.
We do usually force sensible package sharing at schematic entry
(proper halves of a dual opamp, say) when that makes sense. We usually
have a rough channel placement or whatever in mind. If we have, say, a
bus connector that goes to a 16-pin bus transceiver, we will assign
the pins that we know will line up nicely. This is *not*
throw-the-schematic-over-the-wall methodology. We'll sometimes meet
and plan a layout strategy, and sometimes change the design if it
looks like that will help.
If my layout guy has a real problem, he can come to us and we can
alter the schematic to help. But on a multilayer board, you don't have
the crossover dilemmas that you have on a 2-sided board, so pin/gate
swapping isn't as crucial.
John
Robert Latest
> PADS will do a full connectivity check on this
> board in about 2 seconds
What's a connectivity check? I guess it's checking that all power pins are
connected, that there are more than one pins on one net, that no two outputs
share the same net, that a net not only has inputs on it, no open inputs...
that sort of thing? It's called "electrical rule check" in my CAD.
> You can also resequence the ref
> designators on the board
What's a "ref designator"? The "name" of the Part, such as U22, R4?
> We never autoroute,
Ugh. Who does, anyway?
robert
John Larkin
wrote:
>John Larkin wrote:
>
>> PADS will do a full connectivity check on this
>> board in about 2 seconds
>
>What's a connectivity check? I guess it's checking that all power pins are
>connected, that there are more than one pins on one net, that no two outputs
>share the same net, that a net not only has inputs on it, no open inputs...
>that sort of thing? It's called "electrical rule check" in my CAD.
It's a full check of the pcb connections against the schematic
netlist. That's a little more extensive than what you describe.
>
>> You can also resequence the ref
>> designators on the board
>
>What's a "ref designator"? The "name" of the Part, such as U22, R4?
The "R4" is what we call a "reference designator". Each part can have
other attributes, like
type = RES/0805
value = 10K
HTI# = 17213 (our stock number)
decal = 0805
>
>> We never autoroute,
>
>Ugh. Who does, anyway?
I guess some people do. Hell, routing is too important to be left to a
machine.
John
Robert Latest
> It's a full check of the pcb connections against the schematic
> netlist. That's a little more extensive than what you describe.
Ah I see. I was unaware of that because what I use (cheap EAGLE) does it
implicitly.
> I guess some people do. Hell, routing is too important to be left to a
> machine.
Especially if you're as anal about the aesthetics of the result as I am
(and from what I've heard you say, you too).
robert
SioL
>> I guess some people do. Hell, routing is too important to be left to a
>> machine.
>
> Especially if you're as anal about the aesthetics of the result as I am
> (and from what I've heard you say, you too).
>
> robert
I even care about the colour of say thru-hole "folien" caps, sometimes you have
a choice. Its almost sick when you're prepared to pay a tiny bit more to have
the better looking colour, than again some customers do appreciate that :)
SioL
John Larkin
wrote:
We sell VME boards, where all the parts are in plain sight... no
enclosure. So we care a lot about the beauty of the board: colors,
placement, lettering, trace flow. It's art.
John
SioL
> enclosure. So we care a lot about the beauty of the board: colors,
> placement, lettering, trace flow. It's art.
>
> John
There's true beauty in a nicely laid-out board.
I guess that makes us certified geeks.
SioL
David L. Jones
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Thu, 24 May 2007 18:51:42 +0200, "SioL" <Sio_spa...@same.net>
> wrote:
>
>
>
> >"Robert Latest" <boblat...@yahoo.com> wrote in messagenews:slrnf5b8us.3...@kir.physnet.uni-hamburg.de...
>
> >>> I guess some people do. Hell, routing is too important to be left to a
> >>> machine.
>
> >> Especially if you're as anal about the aesthetics of the result as I am
> >> (and from what I've heard you say, you too).
>
> >> robert
>
> >I even care about the colour of say thru-hole "folien" caps, sometimes you have
> >a choice. Its almost sick when you're prepared to pay a tiny bit more to have
> >the better looking colour, than again some customers do appreciate that :)
>
> >SioL
>
> We sell VME boards, where all the parts are in plain sight... no
> enclosure. So we care a lot about the beauty of the board: colors,
> placement, lettering, trace flow. It's art.
If for aesthetics or some other reason you want to hide the trackwork
then black solder mask is the way to go. Looks more like a finished
product than a bare PCB. Very nice when combined with copious amounts
of gold flash.
Dave.
Haude Daniel
> We sell VME boards, where all the parts are in plain sight... no
> enclosure. So we care a lot about the beauty of the board: colors,
> placement, lettering, trace flow. It's art.
Absolutely. I often do mechanical design as well, and the same rules
apply. Even when the device in question is eventually buried in some
vacuum chamber and (ideally) never sees the light of day again. I
think things that look shitty can't work well: Good looks don't
necessarily imply high functionality, but if something turns out to
be crap after all -- well, at least it looks good. As long as you
never compromise functionality for beauty, I've found this to be a
good design strategy. And the mech workshop loves you if you turn
in beautiful drawings for beautiful things.
For my latest electronic gadget, see
http://www.nanoscience.de/group_r/members/dhaude/sed/stm-amp.jpg
Part density is very low, but there's an equal amount of stuff (power
supplies, 4000B series control logic, relays) on the bottom. Piggy-
backed and missing components betray the prototypiness of the thing,
as do the almost-non-overlapping mounting screws.
The front panel is CNC milled from red anodized aluminium:
http://www.nanoscience.de/group_r/members/dhaude/sed/front-panel.jpg
Note the holes for accessing the recessed M5 mounting screws which
firmly bolt the device on a UHV flange. The "4mm hex" designation is
pretty tacky and cost me a couple Euros extra, but without it the
holes had an unmotivated look to them that I didn't like.
--Daniel
SioL
> If for aesthetics or some other reason you want to hide the trackwork
> then black solder mask is the way to go. Looks more like a finished
> product than a bare PCB. Very nice when combined with copious amounts
> of gold flash.
>
> Dave.
AND its much harder to copy your design. Just one of the things that puts the thieves
off.
SioL
vasile
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> We recently did a board that has over 1000 parts, including a uP and
> two FPGAs, 8 layers, parts on both sides. Hand checking that would
> probably take two people a week or so, one calling out connections and
> the other tracing them. PADS will do a full connectivity check on this
> board in about 2 seconds, and a full design-rule check in under 10.
And depending what you have previously done (like autorouting a class
of signals
with some impedance restrictions and accordeons generation) will
forgot or not to number the ground connections on planes. Which
omission will be kept till finishing the board...
Pads (2005) is as buggy as any other CAD, maybe you are lucky ?
> We never autoroute, and almost always go with the pins as originally
> assigned on the schematic, ie no pin or gate swapping.
I'm wandering how you're routing 1000 components (saying you have at
least two 1200 balls BGA's on board and every of them with 300
filtering capacitors) and 10-14 layers without autorouting ?
thx,
Vasile
Robert Latest
> On May 23, 9:26 pm, John Larkin
><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> We recently did a board that has over 1000 parts, including a uP and
>> two FPGAs, 8 layers
>> We never autoroute, and almost always go with the pins as originally
>> assigned on the schematic, ie no pin or gate swapping.
>
> I'm wandering how you're routing 1000 components (saying you have at
> least two 1200 balls BGA's on board and every of them with 300
> filtering capacitors) and 10-14 layers without autorouting ?
What in Johns post gave you the idea of 1200 ball BGAs or 10-14
PCB layers?
robert
John Larkin
>On May 23, 9:26 pm, John Larkin
><jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
>> We recently did a board that has over 1000 parts, including a uP and
>> two FPGAs, 8 layers, parts on both sides. Hand checking that would
>> probably take two people a week or so, one calling out connections and
>> the other tracing them. PADS will do a full connectivity check on this
>> board in about 2 seconds, and a full design-rule check in under 10.
>
>And depending what you have previously done (like autorouting a class
>of signals
>with some impedance restrictions and accordeons generation) will
>forgot or not to number the ground connections on planes. Which
>omission will be kept till finishing the board...
Never seen that happen. Every connection on every board is what the
schematic says. When we screw up, it's a genuine design error or
occasionally an incorrect pinout, plainly visible on the schematic.
We don't prototype; we lay out a board, formally release it as rev A,
and have manufacturing build a couple of units to test. Most of the
time, we can sell the rev A.
>Pads (2005) is as buggy as any other CAD, maybe you are lucky ?
We're using Pads PowerPCB V5, which appears to have no bugs and
doesn't crash. Software this good could make a guy stop hating
Windows. When Mentor bought PADS and started migrating users, we
dropped off the support bandwagon.
>
>
>> We never autoroute, and almost always go with the pins as originally
>> assigned on the schematic, ie no pin or gate swapping.
>
>I'm wandering how you're routing 1000 components (saying you have at
>least two 1200 balls BGA's on board and every of them with 300
>filtering capacitors) and 10-14 layers without autorouting ?
As I mentioned, it's an 8-layer board. On this particular board, there
are two fpga's and one uP, but no bga's.
http://www.highlandtechnology.com/DSS/V470DS.html
300 capacitors?!!! We generally use 3 or 4 bypass caps per supply for
each fpga, bga or otherwise. So that's, say, 9 to 12 caps for a Xilinx
3-supply fpga. A single-supply uP deserves 2 or maybe 3.
See pic in abse.
John
John Larkin
Oops, sorry, that one is 6 layers. We've recently done bga's in six,
too.
John
Tom
> JeffM <jef...@email.com> writes:
> > "Installing gEDA/gaf on Windows--the Cygwin way" by werner
>
> For just pcb, Dan has a windows installer I've pre-tested. It's
> mingw-based, no cygwin required.
Hi
Don't suppose you have some kind of link to this do you?
Tried a search around the web, found several references, but all seem
to be related to something called wcalc.
Tom
DJ Delorie
"Pre-tested". He sent it directly to me. If you have mingw
installed, you can build it from the pcb sources - the scripts are
included.
joseph2k
> On 22 May, 07:32, Tom <t...@ts-net.co.uk> wrote:
>> Morning All
>
> [...]
>> The second question....
>>
>> This is kind of related to the first, I'd be interested to know if
>> everyone designs their PCB's from the schematic stage upwards on
>> computers, or whether there are many people creating the PCB layout
>> only?
>>
>> Tom
>
> I've come across a number of commercial designers that still route
> manually. They'll go the circuit diagram route only if the board
> complexity demands it (say 20 or more packages). They say the main
> reason is time saving from not having to fart about creating unique
> library components and the ensuing struggle with third rate diagram
> editors.
There is a company with a good product that i tried and liked a long time
ago. The company is still around and i am thinking of buying a new copy
just to see the upgrades. Yes, my old 286/386 version is still running.
Schematic capture and pwb manual / auto routing. us $995 for the current
version.
--
JosephKK
Gegen dummheit kampfen die Gotter Selbst, vergebens.
--Schiller
Tom
Please believe me, I am trying not to be a pain/stupid here......
I read around amongst the readme's for gEDA PCB, downloaded cygwin/gtk
+/NSIS installed them all and after some leaps of faith and guessing I
managed to get the build going, but it bails out regarding the not
being able to find a new enough version of gtk+ (wants greater the
2.4.0), but I downloaded and as far as I can make out from the
instruction supplied the latest version.
So having read this reply from you I downloaded mingw, well MSYS,
which from the info at the top seemed the right thing to do. Great,
its installed, it runs, as I expected it won't build as it stands
because there is no way that a 3Mb exe is going to have enough in it.
I guess I'm going to need all the gtk libraries again, and the
pcg_config, which was also giving me a problem.
Yes, you're right, I'm not a Linux user, I am however a programmer and
more than proficient with computers. I tried the mailing list on gEDA
site, anything on there about building on Windows is 95% full of
people slating Windows and saying, well in my opinion, we'd rather
shoot ourselves in the foot than allow Windows users to use gEDA.
Please, is there someone out there who can give me a hand on building
this?
If I can get it built, I would even happily upload the finished NSIS
for others and in fact if its as good as it looks I'll even keep a
regular eye on gEDA releases and build each of the new ones and
upload.
Tom
joseph2k
I am not really sure, but i am chasing a similar goal. If i understand
correctly cygwin-X which include an xwindows build environment is supposed
to make it possible. I have enough problems trying to get it to build in
linux. It must be time for me to try again in each environment.