No dual-gate MOSFET models in SPICE??
Paul Burridge
Hi, the subject's pretty much self-explanatory. So why not?
p.
--
"What is now proved was once only imagin'd"
- William Blake, 1793
Fred Bartoli
"Paul Burridge" <red...@waitrose.notthisbit.com> a écrit dans le message
news: 00e74vsk1itpe20kc...@4ax.com...
>
> Hi, the subject's pretty much self-explanatory. So why not?
>
> p.
> --
Are you sure ?
Here is one, among others.
Fred.
.SUBCKT BF981 1 2 3 4
*Drain Gate2 Gate1 Source
*Dual Gate Mosfet
MD1 5 3 4 4 BF981A
MD2 1 2 5 4 BF981B W=50U
.MODEL BF981A NMOS (LEVEL=1 VTO=-1.1 KP=15M GAMMA=3.3U
+ PHI=.75 LAMBDA=3.75M RS=2.2 IS=12.5F PB=.8 MJ=.46
+ CBD=3.43P CBS=4.11P CGSO=240P CGDO=200P CGBO=20.5N)
.MODEL BF981B NMOS (LEVEL=1 VTO=-.9 KP=18M GAMMA=19.08U
+ PHI=.75 LAMBDA=13.75M RD=41.3 IS=12.5F PB=.8 MJ=.46
+ CBD=3.43P CBS=4.11P CGSO=240P CGDO=200P CGBO=14.5N)
* Philips
* N-Channel Depletion DG-MOSFET
.ENDS
Helmut Sennewald
"Fred Bartoli" <fred.bartoli...@free.removethis.fr.invalid>
schrieb im Newsbeitrag news:3e441151$0$280$626a...@news.free.fr...
Hello Fred,
I think Paul was more interested in a symbol that matches his model file.
I have made one in the past and will present it here.
This is an universal model for dual-gate mosfets. One symbol fits
for all with the same pin order.
1.: SOURCE; 2.: DRAIN; 3.: GATE 2; 4.: GATE 1;
If your model has a different pin order, then you have to change
either the pin order in the model file(library) or you make an
additional symbol for this pin order.
I have done thr example with a correction of the pin order in
the model file of Fred's model.
* Pin order changed in BF981 model
.SUBCKT BF981 4 1 2 3
The symbol and some dual-gate mosfet models from Philips are attached.
You have to include the library path in the schematic.
This will be done with a ".include pathname" command.
In this case it is ".include dg_nmos.lib". if the library is
either in your working directory where your schematic is or in the
"lib\sub" directory of SwitcherCADIII.
There are more universal models for subcircuits of different transistor
types available (DGNMOS, NMOS, PMOS, NPN, PNP, OPAMP) at
http://groups.yahoo.com/group/LTspice/files/lib/sub/ .
Especially the universal opamp model is the big time saver if you have
hundreds of vendor models.
Don't change the "U" in the reference designator if you directly want
to probe the current into this node.
Attached are all needed files.
Symbol: xdgnmos.asy
Example: dual_gate.asc
Library: dg_nmos.lib
Best Regards
Helmut
Symbol file xdgnmos.asy
-----------------------
Version 3
SymbolType CELL
LINE Normal 12 13 12 24
LINE Normal 4 20 12 20
LINE Normal 10 13 12 13
LINE Normal 4 13 10 12
LINE Normal 4 13 10 14
LINE Normal 10 12 10 14
LINE Normal 4 4 4 22
LINE Normal 0 20 2 20
LINE Normal 2 14 2 20
LINE Normal 12 6 4 6
LINE Normal 12 0 12 6
LINE Normal 2 12 2 6
LINE Normal 2 4 2 4
LINE Normal 0 12 2 12
WINDOW 0 14 8 Left 0
WINDOW 3 14 18 Left 0
SYMATTR Prefix X
SYMATTR SpiceModel *
SYMATTR Value XDG-NMOS
SYMATTR SpiceLine *
SYMATTR SpiceLine2 *
SYMATTR Description N-Channel MOSFET transistor
PIN 0 20 NONE 0
PINATTR PinName G1
PINATTR SpiceOrder 4
PIN 12 0 NONE 0
PINATTR PinName D
PINATTR SpiceOrder 2
PIN 12 24 NONE 0
PINATTR PinName S
PINATTR SpiceOrder 1
PIN 0 12 NONE 0
PINATTR PinName G2
PINATTR SpiceOrder 3
SwitcherCADIII example file "dual_gate.asc"
-------------------------------------------
Version 4
SHEET 1 1372 696
WIRE 496 240 496 96
WIRE 496 336 496 464
WIRE 448 320 400 320
WIRE 352 320 352 352
WIRE 224 352 224 288
WIRE 224 288 400 288
WIRE 496 96 224 96
WIRE 224 96 224 128
WIRE 224 208 224 240
WIRE 352 432 352 464
WIRE 224 432 224 464
WIRE 976 240 976 96
WIRE 976 336 976 464
WIRE 928 288 880 288
WIRE 928 320 880 320
WIRE 976 96 736 96
WIRE 400 288 448 288
WIRE 400 320 352 320
WIRE 736 240 736 96
WIRE 736 336 736 464
WIRE 688 288 640 288
WIRE 688 320 640 320
WIRE 736 96 496 96
WIRE 1216 240 1216 96
WIRE 1216 336 1216 464
WIRE 1168 288 1120 288
WIRE 1168 320 1120 320
WIRE 1216 96 976 96
FLAG 224 240 0
FLAG 352 464 0
FLAG 224 464 0
FLAG 496 464 0
FLAG 976 464 0
FLAG 880 288 g2
FLAG 880 320 g1
FLAG 400 288 g2
FLAG 400 320 g1
FLAG 736 464 0
FLAG 640 288 g2
FLAG 640 320 g1
FLAG 496 96 d
FLAG 1216 464 0
FLAG 1120 288 g2
FLAG 1120 320 g1
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\x_models\xdgnmos 928 240 R0
SYMATTR InstName U3
SYMATTR Value BF994S
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\voltage 352 336 R0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\voltage 224 112 R0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\voltage 224 336 R0
SYMATTR InstName V2
SYMATTR Value 4
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\x_models\xdgnmos 688 240 R0
SYMATTR InstName U2
SYMATTR Value BF998
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\x_models\xdgnmos 448 240 R0
SYMATTR InstName U1
SYMATTR Value BF992
SYMBOL F:\PROGRAMME\LTC\SWCADIII\lib\sym\x_models\xdgnmos 1168 240 R0
SYMATTR InstName U4
SYMATTR Value BF981
TEXT 184 48 Left 0 !.include dg_nmos.lib
TEXT 182 16 Left 0 !.dc V1 -1 0.5 0.01
Model file "dg_nmos.lib"
------------------------
* BF992 SPICE MODEL JANUARY 1996 PHILIPS SEMICONDUCTORS
* ENVELOPE SOT143
* 1.: SOURCE; 2.: DRAIN; 3.: GATE 2; 4.: GATE 1;
.SUBCKT BF992 1 2 3 4
L10 1 10 0.12N
L20 2 20 0.12N
L30 3 30 0.12N
L40 4 40 0.12N
L11 10 11 1.20N
L21 20 21 1.20N
L31 30 31 1.20N
L41 40 41 1.20N
C13 10 30 0.085P
C14 10 40 0.085P
C21 10 20 0.017P
C23 20 30 0.085P
C24 20 40 0.005P
D11 42 11 ZENER
D12 42 41 ZENER
D21 32 11 ZENER
D22 32 31 ZENER
RS 10 12 100
MOS1 61 41 11 12 GATE1 L=2E-6 W=2200E-6
MOS2 21 31 61 12 GATE2 L=3.0E-6 W=2200E-6
.MODEL ZENER D BV=10 CJO=1.2E-12 RS=10
.MODEL GATE1
+ NMOS LEVEL=3 UO=904.9 VTO=-0.2051 NFS=300E9 TOX=60E-9
+ NSUB=3E15 VMAX=140E3 RS=2.0 RD=2.0 XJ=500E-9 THETA=0.11
+ ETA=0.2095 KAPPA=0.6488 LD=0.3E-6
+ CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
.MODEL GATE2
+ NMOS LEVEL=3 UO=600 VTO=-0.2051 NFS=300E9 TOX=60E-9
+ NSUB=3E15 VMAX=100E3 RS=2.0 RD=2.0 XJ=500E-9 THETA=0.11
+ ETA=0.06 KAPPA=2 LD=0.3E-6
+ CGSO=0.3E-9 CGDO=0.3E-9 CBD=1.467E-12 CBS=0.5E-12
.ENDS BF992
* BF998 SPICE MODEL OCTOBER 1993 PHILIPS SEMICONDUCTORS
* ENVELOPE SOT143
* 1.: SOURCE; 2.: DRAIN; 3.: GATE 2; 4.: GATE 1;
.SUBCKT BF998 1 2 3 4
L10 1 10 0.12N
L20 2 20 0.12N
L30 3 30 0.12N
L40 4 40 0.12N
L11 10 11 1.20N
L21 20 21 1.20N
L31 30 31 1.20N
L41 40 41 1.20N
C13 10 30 0.085P
C14 10 40 0.085P
C21 10 20 0.017P
C23 20 30 0.085P
C24 20 40 0.005P
D11 42 11 ZENER
D12 42 41 ZENER
D21 32 11 ZENER
D22 32 31 ZENER
RS 10 12 100
MOS1 61 41 11 12 GATE1 L=1.1E-6 W=1150E-6
MOS2 21 31 61 12 GATE2 L=2.0E-6 W=1150E-6
.MODEL ZENER D BV=10 CJO=1.2E-12 RS=10
.MODEL GATE1
+ NMOS LEVEL=3 UO=600 VTO=-0.250 NFS=300E9 TOX=42E-9
+ NSUB=3E15 VMAX=140E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
+ ETA=0.06 KAPPA=2 LD=0.1E-6
+ CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
.MODEL GATE2
+ NMOS LEVEL=3 UO=600 VTO=-0.250 NFS=300E9 TOX=42E-9
+ NSUB=3E15 VMAX=100E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
+ ETA=0.06 KAPPA=2 LD=0.1E-6
+ CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
.ENDS BF998
* BF998WR SPICE MODEL OCTOBER 1993 PHILIPS SEMICONDUCTORS
* ENVELOPE SOT343R
* 1.: SOURCE; 2.: DRAIN; 3.: GATE 2; 4.: GATE 1;
.SUBCKT BF998WR 1 2 3 4
L10 1 10 0.10N
L20 2 20 0.34N
L30 3 30 0.34N
L40 4 40 0.34N
L11 10 11 1.10N
L21 20 21 1.10N
L31 30 31 1.10N
L41 40 41 1.10N
C13 10 30 0.060P
C14 10 40 0.060P
C21 10 20 0.050P
C23 20 30 0.070P
C24 20 40 0.005P
D11 42 11 ZENER
D12 42 41 ZENER
D21 32 11 ZENER
D22 32 31 ZENER
RS 10 12 100
MOS1 61 41 11 12 GATE1 L=1.1E-6 W=1150E-6
MOS2 21 31 61 12 GATE2 L=2.0E-6 W=1150E-6
.MODEL ZENER D BV=10 CJO=1.2E-12 RS=10
.MODEL GATE1
+ NMOS LEVEL=3 UO=600 VTO=-0.250 NFS=300E9 TOX=42E-9
+ NSUB=3E15 VMAX=140E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
+ ETA=0.06 KAPPA=2 LD=0.1E-6
+ CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
.MODEL GATE2
+ NMOS LEVEL=3 UO=600 VTO=-0.250 NFS=300E9 TOX=42E-9
+ NSUB=3E15 VMAX=100E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
+ ETA=0.06 KAPPA=2 LD=0.1E-6
+ CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
.ENDS BF998WR
* BF994S SPICE MODEL MARCH 1996 PHILIPS SEMICONDUCTORS
* ENVELOPE SOT143
* 1.: SOURCE; 2.: DRAIN; 3.: GATE 2; 4.: GATE 1;
.SUBCKT BF994S 1 2 3 4
L10 1 10 0.12N
L20 2 20 0.12N
L30 3 30 0.12N
L40 4 40 0.12N
L11 10 11 1.20N
L21 20 21 1.20N
L31 30 31 1.20N
L41 40 41 1.20N
C13 10 30 0.085P
C14 10 40 0.085P
C21 10 20 0.017P
C23 20 30 0.085P
C24 20 40 0.005P
D11 42 11 ZENER
D12 42 41 ZENER
D21 32 11 ZENER
D22 32 31 ZENER
RS 10 12 100
MOS1 61 41 11 12 GATE1 L=2E-6 W=1280E-6
MOS2 21 31 61 12 GATE2 L=3.0E-6 W=1280E-6
.MODEL ZENER D BV=10 CJO=1.2E-12 RS=10
.MODEL GATE1
+ NMOS LEVEL=3 UO=750 VTO=-0.4357 NFS=300E9 TOX=60E-9
+ NSUB=3E15 VMAX=140E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
+ ETA=0.1686 KAPPA=2.282 LD=0.3E-6
+ CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
.MODEL GATE2
+ NMOS LEVEL=3 UO=600 VTO=-0.4357 NFS=300E9 TOX=60E-9
+ NSUB=3E15 VMAX=100E3 RS=2.0 RD=2.0 XJ=200E-9 THETA=0.11
+ ETA=0.06 KAPPA=2 LD=0.3E-6
+ CGSO=0.3E-9 CGDO=0.3E-9 CBD=0.5E-12 CBS=0.5E-12
.ENDS BF994S
*.SUBCKT BF981 1 2 3 4
*Drain Gate2 Gate1 Source
* Pin order changed in BF981 model
* 1.: SOURCE; 2.: DRAIN; 3.: GATE 2; 4.: GATE 1;
.SUBCKT BF981 4 1 2 3
*Dual Gate Mosfet
MD1 5 3 4 4 BF981A
MD2 1 2 5 4 BF981B W=50U
.MODEL BF981A NMOS (LEVEL=1 VTO=-1.1 KP=15M GAMMA=3.3U
+ PHI=.75 LAMBDA=3.75M RS=2.2 IS=12.5F PB=.8 MJ=.46
+ CBD=3.43P CBS=4.11P CGSO=240P CGDO=200P CGBO=20.5N)
.MODEL BF981B NMOS (LEVEL=1 VTO=-.9 KP=18M GAMMA=19.08U
+ PHI=.75 LAMBDA=13.75M RD=41.3 IS=12.5F PB=.8 MJ=.46
+ CBD=3.43P CBS=4.11P CGSO=240P CGDO=200P CGBO=14.5N)
* Philips
* N-Channel Depletion DG-MOSFET
.ENDS BF981
Paul Burridge
<HelmutS...@t-online.de> opined thusly:
>
[snip]
THanks, gentlemen. I'm afraid I don't seem to have any BF9** series
devices in my model library and no packages for dual gate devices, it
seems. Can I create a model from the parameters you chaps have been
kind enough to post? I assume all these simulators allow one to import
models from outside?
--
Helmut Sennewald
"Paul Burridge" <red...@waitrose.notthisbit.com> schrieb im Newsbeitrag
news:eeq74v05o2khqcjhe...@4ax.com...
> On Fri, 7 Feb 2003 22:26:44 +0100, "Helmut Sennewald"
> <HelmutS...@t-online.de> opined thusly:
>
> >
> [snip]
>
> THanks, gentlemen. I'm afraid I don't seem to have any BF9** series
> devices in my model library and no packages for dual gate devices, it
> seems. Can I create a model from the parameters you chaps have been
> kind enough to post? I assume all these simulators allow one to import
> models from outside?
>
Hello Paul,
yes, you can import the pure Spice model files but not the symbol files.
My posted symbol file and the circuit demo file are only for SwitcherCADIII
users. Sorry, I forgot that you use another Spice simulator.
Best Regards
Helmut
Paul Burridge
<HelmutS...@t-online.de> opined thusly:
>Hello Paul,
>yes, you can import the pure Spice model files but not the symbol files.
>My posted symbol file and the circuit demo file are only for SwitcherCADIII
>users. Sorry, I forgot that you use another Spice simulator.
>
Thanks anyway, Helmut.
I think my simulator allows me to edit and/or create symbols, so maybe
I can get around it.
Just one other question: the SPICE model for MOSFETS - is there just
the one model for both single and dual-gate devices, or are there two
separate models (one for each type)?
Helmut Sennewald
Hello Paul,
a dual gate mosfet consists of two cascaded mosfets. So the model
needs two mosfets. The Philips models includes additional inductance
and capactitance of the package(pins). A single gate mosfets
needs only one mosfet in the model.
Back to the dual-gate mosfet.
These two lines, amomg others are in the library file.
They used two mosfets as expected.
> > MOS1 61 41 11 12 GATE1 L=1.1E-6 W=1150E-6
> > MOS2 21 31 61 12 GATE2 L=2.0E-6 W=1150E-6
Pin order of SPICE mosfet models GATE1, GATE2 is always
"drain gate source substrate".
Equivalent circuit of the above dual-gate mosfet.
-------------------------------------------------
MOS2
o 21
_|
31 | |
o--| |-- 12 = substrate
| |_
|
o 61
_|
41 | |
o--| |-- 12 = substrate
| |_
|
o 11
MOS1
Hope that helps.
Best Regards
Helmut
Paul Burridge
<HelmutS...@t-online.de> opined thusly:
>Hello Paul,
>a dual gate mosfet consists of two cascaded mosfets. So the model
>needs two mosfets. The Philips models includes additional inductance
>and capactitance of the package(pins). A single gate mosfets
>needs only one mosfet in the model.
So, if I understand the above correctly, there is *no* SPICE model
specifically for a dual-gate MOSFET. Instead, the designer has to
select two single-gate MOSFETs and interconnect them for himself?
Helmut Sennewald
> On Sat, 8 Feb 2003 15:13:14 +0100, "Helmut Sennewald"
> <HelmutS...@t-online.de> opined thusly:
>
> >Hello Paul,
> >a dual gate mosfet consists of two cascaded mosfets. So the model
> >needs two mosfets. The Philips models includes additional inductance
> >and capactitance of the package(pins). A single gate mosfets
> >needs only one mosfet in the model.
>
> So, if I understand the above correctly, there is *no* SPICE model
> specifically for a dual-gate MOSFET. Instead, the designer has to
> select two single-gate MOSFETs and interconnect them for himself?
Hello Paul,
yes that is correct.
The same apllies to TRIAC and SCR. They are mostly modelled with NPN
and PNP transistors.
Best Regards
Helmut
Paul Burridge
<HelmutS...@t-online.de> opined thusly:
>
>"Paul Burridge" <red...@waitrose.notthisbit.com> schrieb im Newsbeitrag
>news:v5p94vs8ujrtou3n1...@4ax.com...
>> On Sat, 8 Feb 2003 15:13:14 +0100, "Helmut Sennewald"
>> <HelmutS...@t-online.de> opined thusly:
>>
>> >Hello Paul,
>> >a dual gate mosfet consists of two cascaded mosfets. So the model
>> >needs two mosfets. The Philips models includes additional inductance
>> >and capactitance of the package(pins). A single gate mosfets
>> >needs only one mosfet in the model.
>>
>> So, if I understand the above correctly, there is *no* SPICE model
>> specifically for a dual-gate MOSFET. Instead, the designer has to
>> select two single-gate MOSFETs and interconnect them for himself?
>
>
>Hello Paul,
>yes that is correct.
>The same apllies to TRIAC and SCR. They are mostly modelled with NPN
>and PNP transistors.
Thanks, Helmut. So does the same situation pertain for darlington
transistors? No specific SPICE model for those either?
Jim Thompson
We seem to be generating confusion over "device models" versus
"subcircuits".
BJT is a *device type* and has a *model*. A Darlington is simply a
combination of two BJT *devices* and can be represented as a
*subcircuit* for simulation purposes.
Likewise a dual-gate MOS device can be represented as a subcircuit.
Keep in mind, given the right software tools, you can make a *device
model* for anything.
Spice includes *device models* for all *common* circuit elements.
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| Jim-T@analog_innovations.com Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
For proper E-mail replies SWAP "-" and "_"
I love to cook with wine. Sometimes I even put it in the food.
Paul Burridge
<Jim-T@analog_innovations.com> opined thusly:
>We seem to be generating confusion over "device models" versus
>"subcircuits".
>
>BJT is a *device type* and has a *model*. A Darlington is simply a
>combination of two BJT *devices* and can be represented as a
>*subcircuit* for simulation purposes.
>
>Likewise a dual-gate MOS device can be represented as a subcircuit.
>
>Keep in mind, given the right software tools, you can make a *device
>model* for anything.
>
>Spice includes *device models* for all *common* circuit elements.
Thanks, Jim. I'm beginning to build up a better picture of things,
now. Earlier in this thread, Helmut posted this equivalent for a DGM
using two discrete single-gate MOSFETs:
MOS2
o 21
_|
31 | |
o--| |-- 12 = substrate
| |_
|
o 61
_|
41 | |
o--| |-- 12 = substrate
| |_
|
o 11
MOS1
So what you're saying is that I simply create a "subcircuit"
consisting of the above, create a symbol for it using the Symbol
Editor in my software, and away I go? Is a dual-gate device really
accurately modeled by combining to single-gate ones? It just seems a
bit too simplistic to my mind.
BTW, Helmut, if you're reading this, to what do the numbered nodes
refer to in the above diagram?
Helmut Sennewald
Hello Paul,
you omitted the important lines below. They decribe the connections
of the two Mosfets MOS1 and MOS2. Look at the 4 numbers behind MOS1
MOS2 . These are the node names(numbers) in my drawing too.
> > > Back to the dual-gate mosfet.
> > > These two lines, amomg others are in the library file.
> > > They used two mosfets as expected.
> > > MOS1 61 41 11 12 GATE1 L=1.1E-6 W=1150E-6
> > > MOS2 21 31 61 12 GATE2 L=2.0E-6 W=1150E-6
> > > Pin order of SPICE mosfet models GATE1, GATE2 is always
> > > "drain gate source substrate".
That order means in this example
MOS1: 61=drain 41=gate 11= source 12=substrate
MOS2: 21=drain 31=gate 61= source 12=substrate
GATE1 and GATE2 are basic SPICE NMOS mosfet models.
L ans W are are the size parameters of that particular mosfet.
Unit of measure is meter[m].
If you have time then you can make a drawing of the whole subcircuit
from the text below. Each number is a node of the circuit.
Put the parts Lx, Cx, Rx, MOS1, MOS2 inbetween.
Best Regards
Helmut
The whole subcircuit from Philips.
----------------------------------
* BF998 SPICE MODEL OCTOBER 1993 PHILIPS SEMICONDUCTORS
* ENVELOPE SOT143
* 1.: SOURCE; 2.: DRAIN; 3.: GATE 2; 4.: GATE 1;
.SUBCKT BF998 1 2 3 4
L10 1 10 0.12N
L20 2 20 0.12N
L30 3 30 0.12N
L40 4 40 0.12N
L11 10 11 1.20N
L21 20 21 1.20N
L31 30 31 1.20N
L41 40 41 1.20N
C13 10 30 0.085P
C14 10 40 0.085P
C21 10 20 0.017P
C23 20 30 0.085P
C24 20 40 0.005P
D11 42 11 ZENER
D12 42 41 ZENER
D21 32 11 ZENER
D22 32 31 ZENER
RS 10 12 100
MOS1 61 41 11 12 GATE1 L=1.1E-6 W=1150E-6
MOS2 21 31 61 12 GATE2 L=2.0E-6 W=1150E-6
.MODEL ZENER D BV=10 CJO=1.2E-12 RS=10
Jim Thompson
I can't speak to the efficacy of this dual-gate subcircuit. I don't
think I've even seen a dual-gate MOSFET for a least 30 years ;-)
Paul Burridge
<HelmutS...@t-online.de> opined thusly:
>Hello Paul,
>you omitted the important lines below. They decribe the connections
>of the two Mosfets MOS1 and MOS2. Look at the 4 numbers behind MOS1
>MOS2 . These are the node names(numbers) in my drawing too.
>
[snip]
THanks again, Helmut. I'm going to take a while to digest and
implement your suggestions. This stuff is a bit over my head for my
current level of experience with SPICE, to be honest. But I'll get
there in the end! I'm nothing if not persistent. :-)
Terry Pinnell
>yes that is correct.
>The same apllies to TRIAC and SCR. They are mostly modelled with NPN
>and PNP transistors.
Helmut: In CircuitMaker there appear to be many available. Here's one
of about 80 100 SCR types, the C106A.
*100V 4A pkg:TO-126 2,3,1
.SUBCKT XC106A 1 2 3
QP 6 4 1 POUT OFF
QN 4 6 5 NOUT OFF
RF 6 4 22.2MEG
RR 1 4 14.8MEG
RGK 6 5 1.12K
RG 2 6 46.2
RK 3 5 16.2M
DF 6 4 ZF
DR 1 4 ZR
DGK 6 5 ZGK
.MODEL ZF D (IS=1.6F IBV=900N BV=100 RS=3.33MEG)
.MODEL ZR D (IS=1.6F IBV=900N BV=133)
--
Terry Pinnell
Hobbyist, West Sussex, UK
Jim Thompson
And don't forget to call models for POUT, NOUT, and DGK ;-)
