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opencores-tri-mode eth MAC
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Ali Imran Siddiqui
2/23/21
Broadcast Problem with Tri mode Ethernet.
Hello Everyone. Can anyone please guide me why my broadcast IP not working with this core. If i ping
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Broadcast Problem with Tri mode Ethernet.
Hello Everyone. Can anyone please guide me why my broadcast IP not working with this core. If i ping
2/23/21
Hua Yu
,
bashid
2
7/14/20
problem for UDP_IP_Core transmittion
did your problem solve? Can you share that part of your code? On Monday, July 23, 2012 at 12:57:04 AM
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problem for UDP_IP_Core transmittion
did your problem solve? Can you share that part of your code? On Monday, July 23, 2012 at 12:57:04 AM
7/14/20
Egor Ibragimov
,
Egor Ibragimov
2
9/17/18
Error while loading design, after compiling is successfully complete
Adding the line `timescale 1 ns / 1 ns solved this error But why it is not in svn trunk? How can I
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Error while loading design, after compiling is successfully complete
Adding the line `timescale 1 ns / 1 ns solved this error But why it is not in svn trunk? How can I
9/17/18
dpaul
,
m11elab...@gmail.com
3
3/16/18
How are people testing this core?
Il giorno martedì 9 febbraio 2016 12:02:12 UTC+1, dpaul ha scritto: For the benefit of others who may
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How are people testing this core?
Il giorno martedì 9 febbraio 2016 12:02:12 UTC+1, dpaul ha scritto: For the benefit of others who may
3/16/18
m11elab...@gmail.com
3/16/18
Help beginner to perform test bench of core
Hello,I'm trying to make test bench with Vivado but without success because Cadence incisive is
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Help beginner to perform test bench of core
Hello,I'm trying to make test bench with Vivado but without success because Cadence incisive is
3/16/18
Clifford Black
11/10/17
-LUT COE file
I cannot locate the subject file. The IP Description states that it is included in the package. Can
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-LUT COE file
I cannot locate the subject file. The IP Description states that it is included in the package. Can
11/10/17
mvo...@googlemail.com
9/29/17
Mistake in preamble and SDF in sending package?
Hi there, During my work with the IP-Core I have made some simulations with ModelSim. I found out,
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Mistake in preamble and SDF in sending package?
Hi there, During my work with the IP-Core I have made some simulations with ModelSim. I found out,
9/29/17
m11elab...@gmail.com
, …
niasu...@gmail.com
5
9/12/17
Errors during synthesis of core 10_100_1000 Mbps tri-mode ethernet MAC on Vivado 2017.1
Hi, altsyncram file for theduram is missing from the core that I have downloaded. Can you please help
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Errors during synthesis of core 10_100_1000 Mbps tri-mode ethernet MAC on Vivado 2017.1
Hi, altsyncram file for theduram is missing from the core that I have downloaded. Can you please help
9/12/17
niasu...@gmail.com
9/12/17
altsynram file is missing
I have downloaded 10_100_1000 Mbps tri-mode ethernet MAC core. In the downloaded zip folder I am not
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altsynram file is missing
I have downloaded 10_100_1000 Mbps tri-mode ethernet MAC core. In the downloaded zip folder I am not
9/12/17
Frans Schreuder
, …
bgd...@googlemail.com
7
3/14/17
AXI4 interface for opencores-tri-mode mac
Hi Frans, have you already made some progress? I would be interested in a cooperation if you still
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AXI4 interface for opencores-tri-mode mac
Hi Frans, have you already made some progress? I would be interested in a cooperation if you still
3/14/17
Saul Duran
,
Roberto Alcântara
2
1/23/17
hangs at "waiting for opencores.org"
Everything is fine here from Brazil. Cheers, - Roberto Em seg, 23 de jan de 2017 às 11:00, Saul Duran
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hangs at "waiting for opencores.org"
Everything is fine here from Brazil. Cheers, - Roberto Em seg, 23 de jan de 2017 às 11:00, Saul Duran
1/23/17
Mark Kaper
, …
Thomas Donner
4
9/27/16
bug fixes, implementatien on virtex 6 and virtex 7.
Hi Are there any updates for this files in between. I also plan to use this core with Xilinx. Maybe I
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bug fixes, implementatien on virtex 6 and virtex 7.
Hi Are there any updates for this files in between. I also plan to use this core with Xilinx. Maybe I
9/27/16
Thomas Donner
9/5/16
Timing Constraints
Hi I found this core on opencores.org. I was looking for an IP-core which I can use to adapt it to
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Timing Constraints
Hi I found this core on opencores.org. I was looking for an IP-core which I can use to adapt it to
9/5/16
钱坤
9/4/16
Where can I get LDV5.1 for Linux
I know it is a naive question. But I have searched for a while on the Google and I do not find the
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Where can I get LDV5.1 for Linux
I know it is a naive question. But I have searched for a while on the Google and I do not find the
9/4/16
Srkan Tran
4
5/30/16
Gbit_Core_Usage
follow the core specification document and try to generate waves that corresponds to tx_clk, tx_en,
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Gbit_Core_Usage
follow the core specification document and try to generate waves that corresponds to tx_clk, tx_en,
5/30/16
Donne Chu
3/5/16
MIIM module
I found some signals in the MIIM module have no drivers, like Divider, CtrlData, Rgad, Fiad, NoPre,
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MIIM module
I found some signals in the MIIM module have no drivers, like Divider, CtrlData, Rgad, Fiad, NoPre,
3/5/16
s1596...@gmail.com
, …
dpaul
4
1/8/16
Operation System Problem
Hello Gao, That is indeed a barrier. Have you already replaced this with Verilog file read? If yes, I
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Operation System Problem
Hello Gao, That is indeed a barrier. Have you already replaced this with Verilog file read? If yes, I
1/8/16
liu kerry
, …
dpaul
4
1/8/16
Load failed "ip_32w_gen.dll"
Hello, I am trying to adapt this core and its TB for Vivado 2015.4. During behav sim I run into the
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Load failed "ip_32w_gen.dll"
Hello, I am trying to adapt this core and its TB for Vivado 2015.4. During behav sim I run into the
1/8/16
dpaul
2
1/7/16
Generating a Xilinx dual-port BRAM for the tx/rx FIFO implementation (Artix7)
I think I got my answer after reading the datasheet Block Memory Generator v8.2, pg058-blk-mem-gen.
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Generating a Xilinx dual-port BRAM for the tx/rx FIFO implementation (Artix7)
I think I got my answer after reading the datasheet Block Memory Generator v8.2, pg058-blk-mem-gen.
1/7/16
Pankaj Mazumder
, …
dpaul
3
1/5/16
Basic Info on this IP
Hi Pankaj. If you are still active and have successfully done your uni project, then can you please
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Basic Info on this IP
Hi Pankaj. If you are still active and have successfully done your uni project, then can you please
1/5/16
Gustavo Maia
11/30/15
Promiscuous Mode?
Hi all, I am interested in using this core for a school project. I want to do a network monitor, with
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Promiscuous Mode?
Hi all, I am interested in using this core for a school project. I want to do a network monitor, with
11/30/15
WachaG
, …
tamirci
7
8/19/15
tri-mode eth MAC signals
Hi Amir, You say here that "look at page 26 and 27 on specification". I downloaded spec and
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tri-mode eth MAC signals
Hi Amir, You say here that "look at page 26 and 27 on specification". I downloaded spec and
8/19/15
EthMcStone
, …
tamirci
7
7/29/15
MDIO interface
Hi EthMcStone, You indicate this core is working. Could you please provide TX side wrapper? regards
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MDIO interface
Hi EthMcStone, You indicate this core is working. Could you please provide TX side wrapper? regards
7/29/15
youngill kim
,
Srkan Tran
2
7/20/15
phy chip
you can use Marvell 88E1111 PHY. regards
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phy chip
you can use Marvell 88E1111 PHY. regards
7/20/15
michael....@googlemail.com
, …
Xana
6
6/30/15
Loopback
Hi Paul, Is this part of code helping the loop-back between Rx and Tx? What is the line_loop_en for
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Loopback
Hi Paul, Is this part of code helping the loop-back between Rx and Tx? What is the line_loop_en for
6/30/15
Paul Bar
,
M@work
7
1/20/15
Packet reception stops after some time?
I remember having added 2 FF to align the rx_dv with the rx_err. So as you say my two problems might
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Packet reception stops after some time?
I remember having added 2 FF to align the rx_dv with the rx_err. So as you say my two problems might
1/20/15
Jonathan Gao
12/19/14
Re: Tx_mac_BE
Yes. You got it. The BE is only valid together with EOP. This assume all the data are continus 4
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Re: Tx_mac_BE
Yes. You got it. The BE is only valid together with EOP. This assume all the data are continus 4
12/19/14
Paul Bar
,
Jonathan Gao
2
12/19/14
Re: Connecting to opencores 1G UDP/IP Stack
Try to leverage the asynmatric asynchronous fifo. For example, write in as 32bit data width with
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Re: Connecting to opencores 1G UDP/IP Stack
Try to leverage the asynmatric asynchronous fifo. For example, write in as 32bit data width with
12/19/14
Paul Bar
10/8/14
Clock frequencies clarification
The clock domain crossing in the Rx_FF: I had problems when using Clk_mac =125MHz, the Clk_SYS =
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Clock frequencies clarification
The clock domain crossing in the Rx_FF: I had problems when using Clk_mac =125MHz, the Clk_SYS =
10/8/14
The Guy
,
Paul Bar
2
10/7/14
Source MAC Address
You need to build it yourself. You do not need to add the ethernet frame delimiter and checksum, but
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Source MAC Address
You need to build it yourself. You do not need to add the ethernet frame delimiter and checksum, but
10/7/14