finding JTAG, electrical patterns via oscilloscope?

[cyphunk]

What types of electrical layouts on the JTAG pins can be expected when
checking with an oscilloscope? I suspect a 10 pin header on a board i
have is for JTAG from an Altera FPGA chip. The two ground pins common
for Altera JTAG are in the same place on my board (pin 2 and 10).
Vref (pin 4) is also giving a constant voltage (3.3v). What other
similarities should I find, what other electrical characteristics are
common of JTAG lines when looking with a scope.

Can I assume that when not connected and when looking under a scope
that a pin meant for...
- CLK would be open, held low, not connected since it is meant for
input by board?
- Vref would be giving a constant voltage?
- TDO would be giving a constant voltage similar to the Vref pin?
- TMS would be open/low/not-connect since meant as input by board?
- TDI would be open/low/not-connect since meant as input by board?


I have already attempted to plug up an Amontec JTAGkey with urjtag and
openocd software but I am getting some errors with the connection that
I wont get into here. Not much has been defined by the communities
for either openocd or urjtag for the altera chips so before I dig in
deeper I thought I could first confirm the assumption of the JTAG
header looking at things electrically.

[chf...@columbia.edu]

So you are trying to connect to an actual altera FPGA? Are the pins
exposed (i.e. some kind of QFP, rather than BGA?)? Any input pin
should just be "high impedance", and the TDO pin will probably default
to zero. JTAG works off of a state machine controlled by the clock and
TMS pins, so it is possible to put the internal FSM into a state (data
shift, i think?) where it is basically a huge shift register with TDI
as the input and TDO as the output, so if you start shifting in data,
eventually you can verify it coming out the other side if it is all
working properly. I *think* the state machine might be universal, but
I'm not sure. Xilinx' IMPACT tool as a nice Debug GUI for letting you
manually "walk" the state machine by toggling pins, and it keeps track
with a nice diagram. Hope that helps
-chris

[Ben Simpson]

Do you have the datasheet? It would tell you the default state for these pins. I agree with Chris. Inputs are highZ, outputs maybe have weak pullups/downs.
Ben

- CLK would be open, held low, not connected since it is meant for
input by board?
- Vref would be giving a constant voltage?
- TDO would be giving a constant voltage similar to the Vref pin?
- TMS would be open/low/not-connect since meant as input by board?
- TDI would be open/low/not-connect since meant as input by board?

[Jeff Keyzer]

The "more money than skills/time" approach would be to acquire another
board, remove the FPGA, and look for continuity between the JTAG pads
of the IC and the 10 pin header.

I am guilty of this. ;-)

(Or if you could remove the FPGA from the board you have, provided you
can put it back with reasonable certainty it will still work.)

Jeff Keyzer
je...@mightyohm.com

[mmelnick]

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[Ben Simpson]

badass

[mmelnick]

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