Need a few pages of Chinese Loongson2f doc (errata) translated to English
Daniel Clark
translated to English.
Multiple translations probably wouldn't be a bad thing.
Also I'll re-plug "Loongson port about to make 4.7" -
http://ur1.ca/nztq - very interesting article.
BTW I think I remember reading that ST was not involved in loongson
any more - is that correct?
---------- Forwarded message ----------
From: Miod Vallat <mi...@online.fr>
Date: Mon, Mar 1, 2010 at 9:22 AM
Subject: Re: Loongson2f errata in Chinese - where?
To: Daniel Clark <dcl...@pobox.com>
> ( Re: http://marc.info/?l=openbsd-cvs&m=126704563830890&w=2 )
>
> Could I get a copy of or URL to the Loongson 2F errata in Chinese? I
> know people who would translate it to English.
What would be better is to convince Loongson to produce a translated
document, or get ST to do it and publish it.
The chinese manual for the 2F is freely available at:
http://www.loongson.cn/uploadfile/file/20080821113149.pdf
[now also at http://ur1.ca/nzsz -DC]
The pages which are not present in the english edition published by ST
are:
- chapter 15 (errata), pdf page 162
- table 11-3 (PCIX ISR registers description), pdf pages 123 to 126.
Thanks,
--
Daniel JB Clark | Free Software Activist | http://pobox.com/~dclark
yajin
> - table 11-3 (PCIX ISR registers description), pdf pages 123 to 126.
I will translate these parts into English tomorrow morning if you can
wait for a while. It's 11 PM now in my timezone.
Thanks & Regards
yajin
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yajin
The following is the translation of chapter 15. About the table 11-3,
do you mean the description of ISR40 to ISR 58 in page 112-115?
In fact the page [1] has given the description and the workaround of
the bugs in chapter 15.
[1] http://groups.google.com/group/loongson-dev/web/loongson2f-cpu-bugs
Translation:
15 Errata: Issue of Out-of-order in loongson
In loongson 2F, because of the branch prediction, sometimes the CPU
may fetch the instructions from some unexpected area( for example I/O
space). It is an invalid operation. There are two ways for the CPU to
choose the branch target. The first one is predicting the branch
target according to the branch target history. The second one is
calculating the branch target by the ALU. There are most 8
instructions in the instruction window at the same time in loongson
2f( Remember the loongson 2f is superscalar, right?). Hence, the
branch target of an indirect branch(such as jr) could be got(may be
predicted by the branch target history) earlier and the instrctions of
the branch target could be prefetched even if there are branch
instructions before it. As a result, it is possible to fetch the
instructions from I/O region( say out-of the physical address range of
[0- 0x100000]) in kernel model because of the instruction prefetch of
the branch target.
There are some suggestions to prevent prefetching instructions from
the I/O region in kernel mode.
(1) When switching from user model to kernel model, you should flush
the branch target history such as BTB and RAS.
(2) Doing some tricks to the indirect branch target to make sure that
the indirect branch target can not be in the I/O region.
yajin
Wu Zhangjin
[...]
>
> There are some suggestions to prevent prefetching instructions from
> the I/O region in kernel mode.
>
> (1) When switching from user model to kernel model, you should flush
> the branch target history such as BTB and RAS.
Here includes the related source code in linux:
the commit 13cc3656ca9f4d651c9fb3ed2a7ce27b47c51134 in the rt4ls git
repo:
http://dev.lemote.com/cgit/rt4ls.git/commit/?id=13cc3656ca9f4d651c9fb3ed2a7ce27b47c51134
> (2) Doing some tricks to the indirect branch target to make sure that
> the indirect branch target can not be in the I/O region.
>
Please refer to the "JUMP issue" part and the related
fix_loongson2f_jump function in
http://sourceware.org/ml/binutils/2009-11/msg00387.html
Regards,
Wu Zhangjin
yajin
>> do you mean the description of ISR40 to ISR 58 in page 112-115?
>
ISR_40
31, tar_read_io, rw(write 1 to clear this bit), 0, The target has
received the access request to the I/O region or the region which can
not be prefetched.
30, tar_read_discard, rw(write 1 to clear this bit), 0, The delay
request of the target has been discarded.
29, tar_resp,delay, rw,0, When the delay/split will be given to
target. 0: After the delay. 1: immediately
28,tar_delay_retry,rw,0, The method used for retry. 0: according to
the internal logic(refer to bit 29). 1: retry immediately.
27, tar_read_abort_en, rw,0, If the read request to target is
time-out, whether it will response with target-abort.
16:25, reserved
24, tar_write_abort_en,rw,0, If the write request to target is
time-out, whether it will response with target-abort.
23, tar_master_abort, rw,0, Is the time-out of the delay of
master-abort target enabled?
22:20, tar_subseq_timeout, rw,000. 000: 8 cycles. Other value: not supported.
19:16,tar_init_timeout,rw,0000. The timeout of the init target delay.
In PCI Model, 0: 16 cycles. 1-7: disable the counter, 8-15:8-15
cycles. In PCIX model, the timeout is fixed to 8 cycles. (I can not
understand the following description).
15:4,tar_pref_boundary, rw,000h. The boundary of the prefetch in
16bytes. FFF:64KB to 16 bytes. FFE:64KB to 32 bytes. FF8:64KB to 128
bytes.
3,tar_pref_bound_en,rw,0. 0: prefetch to the boundary of devices. 1:
use the configuration in tar_pref_boundary.
2, Rserved
1, tar_splitw_ctrl,rw,0, 0:block all the access expect Posted memory
write. 1: block all the access until the split finish the operation of
disable master access time-out
0,mas_lat_timeout,rw,0. 0: master access time-out is allowed. 1:
master access time-out is not allowed.
ISR_44
31:0, Reserved
ISR_48,
31:0,tar_pending_seq,rw,0, The bits vector of the sequence number of
the request which has not been finished by the target. Write 1 to the
bit to clear the bit.
ISR_4C,
31:30, Reserved
29, mas_write_defer, rw,0, The read of following instruction can go
ahead to the current unfinished write. (only effective to PCI)
28,mas_read_defer,rw,0,The write and read of following instruction can
go ahead to the current unfinished read. (only effective to PCI)
27,mas_io_defer_cnt,rw,0,
26:24,mas_read_defer_cnt,rw,010, The max number of the read operation
which can go ahead. (only effective to PCI) 0:8. 1-7:1-7.
23:16,err_seq_id,ro,00h, The error sequence number of target/master
15.err_type,ro,0. The command type of the target/master error.
14,err_module,ro,0. The error module. 0: Target. 1:master
13,system_error,rw,0. The system error of target/master. Write 1 to clear.
12,data_parity_error,rw,0, The data CRC error of target/master. Write
1 to clear.
11,ctrl_parity_error,rw,0, The address CRC error of target/master.
Write 1 to clear.
10:0, Rserved
ISR_50,
31:0,mas_pending_seq,rw,0. The bits vector of the sequence number of
the request which has not been finished by the master. Write 1 to the
bit to clear the bit.
ISR_54
31:0,mas_split_err,rw,0, The bits vector of the sequence number of the
request which is returned by split.
ISR_58
31:30,Rserved
29:28,tar_split_priority,rw,0. The priority returned by target split.
0 is the highest and 3 is the lowest.
27:26,mas_req_priority,rw,0. The priority of the master. The bits
vector of the sequence number of the request which has not been
finished by the master.
25,Priority_en. rw,0. The algorithms used in arbitration between
master access and target split. 0: fixed priority. 1: Round-robin
24:18, Reserved
17,mas_retry_aborted,rw,0, The retry of master retry has been
canceled. Write 1 to clear.
16,mas_trdy_timeout,rw,0,0, The number of timeout of the master TRDY.
15:8,mas_retry_value,rw,00h, The number of the master retry. 0: always
retry. 1-255: 1-255.
7:0,mas_trdy_count,rw,00h, The count of the master TRDY. 0:The counter
is disabled. 1-255:1-255.
yajin
On Tue, Mar 2, 2010 at 1:20 PM, Miod Vallat <mi...@online.fr> wrote:
>> The following is the translation of chapter 15. About the table 11-3,
>> do you mean the description of ISR40 to ISR 58 in page 112-115?
>
> Yes.
>
>> In fact the page [1] has given the description and the workaround of
>> the bugs in chapter 15.
>>
>> [1] http://groups.google.com/group/loongson-dev/web/loongson2f-cpu-bugs
>
> But you'll notice that this message does not mention the need to clear
> RAS, while chapter 15 does.
>