Bus Speeds doc & question
Harvey Taylor
Tacked on below is a table of some bus speeds I have collected from
here & comp.arch and various mags. I take these with a large grain of
salt.
What I wonder is how do people come up with such figures?
Empirical data? Theoretical? I would guess
(Clock/Clocks_per_transfer)*Width/8 = MBytes/s, while ignoring wait
states & bus contention?
<-Harvey
===========================================================
Model Clock Width Logic Speed
(MHz) (bits) Level/Type MBytes/s
===========================================================
ChipBus 7.14 16 TTL
Zorro II 7.14 16 TTL 3.75
Zorro III 16 32 TTL 12
Zorro III 25 32 TTL 20
AT Bus 4.77 16 TTL 4
NuBus 32 TTL 20
NuBus (Block) 32 TTL 37.5
MCA 32 TTL 20
MCA (Burst) 32 TTL 40
MCA (Extended0) 64 TTL 80
MCA (Extended1) 64 BTL 160
S-100
VMEBus 40
MultiBus 40
MIPS R6000 67 32 ECL 270
FutureBus 32 BTL 100
FutureBus 256 BTL 3200
===========================================================
"Joyous distrust is a sign of health.
Everything absolute belongs to pathology." - Nietzsche
Harvey Taylor Meta Media Productions
uunet!van-bc!rsoft!mindlink!Harvey_Taylor
a1...@mindlink.UUCP
Rostyk Lewyckyj
>
> Tacked on below is a table of some bus speeds
>
> Model Clock Width Logic Speed
> (MHz) (bits) Level/Type MBytes/s
> ===========================================================
> ChipBus 7.14 16 TTL
> Zorro II 7.14 16 TTL 3.75
> Zorro III 16 32 TTL 12
> Zorro III 25 32 TTL 20
> NuBus (Block) 32 TTL 37.5
> MCA 32 TTL 20
> MCA (Burst) 32 TTL 40
(with no apologies, I have shortened the above table to close
competitors of the AMIGA) Now on with my tangent :-)
A long time ago (Just after A2000 was released) I posted a tongue
in cheek prediction about when the A3000 would come out, and what
it would have. Since C= had just changed the bus and added the IBM/PC
bus, I wrote that the A3000 would use the NuBus for compatability
with the Mac (easy use of Mac expansion cards :-) ). Apparently
Mr. Haynie took the posting seriously, because he wrote me asking
why I thought he would use the NuBus and criticised it as being slow.
By the above figures, if they mean anything, Zorro III is being rated
slower than the NuBus and MCA. Personally I doubt some of these
numbers, although I have seen those for MCA in comp.arch.
First the bus speed/frequency is separate from the CPU clock speed,
so the clock speed in col 2 is not relevant. Second, I have heard
in various discussions that: the Amiga bus(es) all run at the 7.xx Mhz
multiple of the NTSC/TV frequency; the NuBus runs at around 10 Mhz;
and the old PC busses ran 8-10 Mhz., which caused problems with some
expansion cards that were sometimes too slow for machines with cranked
up busses. Also the bus clocks can not just be cranked up beyond their
design limits.
In any case whatever the bus speed may be what matters in the end is
benchmarked thruput on the job stream of your choice. So far posted
repeatable head to head comparison benchmark results are sadly lacking
in the network mcbyc computer wars.
Nevertheless in evaluating a computer design as an object d art, one
of the goodnes criteria is balance. i.e. under the intended workload
what proportion of the time is some component being held up from doing
its intended task by the inadequacy of another component. Call it
bottleneck analysis. For example a 33 Mhz 80386 is largely wasted
in an old IBM/PC. For example 256K memory on the original MAC was
a bad decision. So my question is. What are the bottlenecks on the
A3000? and specifically wrt. the ZORRO III bus
Given an A3000/25 with lots of memory doing the following types
of element by element operations on largish, (100 x 100), matrices:
A + B --> C for 16 bit integers
A + B --> C for 32 bit integers
A * B --> C for 16 bit integers
A * B --> C for 32 bit integers
similarly for 32 bit floating point numbers
similarly for double precision floating point
similarly for IEEE floating point
What fraction of the time will the cpu be idle waiting for operands
from memory when doing A + B ? and what fraction of the time will
the bus be idle waiting on the cpu for A * B or A/B ?
Assume the system is otherwise idle, screen is blanked, and no
extraneous i/o. Assume the coding is in tight assembler.
Of course in normal operation other things are going on so the
challange to those in the know, if they are willing to comment is?
Tell us if and why you think the A3000 is technically a well designed
and properly balanced machine.
-----------------------------------------------
Reply-To: Rostyslaw Jarema Lewyckyj
urj...@ecsvax.UUCP , urj...@unc.bitnet
or urj...@uncvm1.acs.unc.edu (ARPA,SURA,NSF etc. internet)
tel. (919)-962-6501
Harvey Taylor
writes:
[table deleted]
>(with no apologies, I have shortened the above table to close
>competitors of the AMIGA)
Pity. This group seems to need the perspective.
> Now on with my tangent :-)
[...]
>By the above figures, if they mean anything, Zorro III is being rated
>slower than the NuBus and MCA. Personally I doubt some of these
>numbers, although I have seen those for MCA in comp.arch.
I doubt them too. How are they generated?
[...]
>In any case whatever the bus speed may be what matters in the end is
>benchmarked thruput on the job stream of your choice. So far posted
>repeatable head to head comparison benchmark results are sadly lacking
>in the network mcbyc computer wars.
Anybody done this?
[...]
>What fraction of the time will the cpu be idle waiting for operands
>from memory when doing A + B ? and what fraction of the time will
>the bus be idle waiting on the cpu for A * B or A/B ?
Is it not the case that whenever the Execution Unit is tied up
with a many cycle op such as MULT that the Bus Controller will take
the opportunity to start refilling the caches?
"Accurate reckoning - the entrance into the knowledge of all existing
things and all obscure secrets." -Ahmes the scribe, ca.1700 BC
Harvey Taylor
|
|In article <1990May23.0...@uncecs.edu> urj...@uncecs.edu
|(Rostyk Lewyckyj) writes:
|>In article <18...@mindlink.UUCP>, a1...@mindlink.UUCP (Harvey Taylor) writes:
|
|>Since C= had just changed the bus and added the IBM/PC
|>bus, I wrote that the A3000 would use the NuBus for compatability
|>with the Mac (easy use of Mac expansion cards :-) ). Apparently
|>Mr. Haynie took the posting seriously, because he wrote me asking
|>why I thought he would use the NuBus and criticised it as being slow.
Please note that I didn't write any of this >quoted material.
|Yeah, I remember that. And what that table doesn't show you is that
|68030 to NuBus interface on the Mac IIs runs about 5 MB/s.
How do you know this? I'm not doubting you in particular, I'm just
looking for an EE101 answer to how to measure &/calculate bus speeds.
| [...]
| I suppose if I sat down and
|calculated maximum theoretical Zorro III speed, I'd tell you that it maxes
|out at 50 MB/s for a standard full cycle, over 150 MB/s for a full burst
|cycle. But that's simply based on the specification;
|
| [...]
|That says nothing about how fast other bus masters might go, nor how fast a
|future Amiga may be able to drive Zorro III.
Same questions...
Dave Haynie
>Since C= had just changed the bus and added the IBM/PC
>bus, I wrote that the A3000 would use the NuBus for compatability
>with the Mac (easy use of Mac expansion cards :-) ). Apparently
>Mr. Haynie took the posting seriously, because he wrote me asking
>why I thought he would use the NuBus and criticised it as being slow.
Yeah, I remember that. And what that table doesn't show you is that
68030 to NuBus interface on the Mac IIs runs about 5 MB/s. The 12 MB/s
and 20 MB/s quoted above are real numbers based on the CPU to bus
interface on an A3000. Theoretical speeds may go faster, because Zorro
III top end bus speed is largely based on the particular implementation of
the bus controller. That chart also doesn't mention any figures on
Zorro III running Multiple Transfer Cycles.
>By the above figures, if they mean anything, Zorro III is being rated
>slower than the NuBus and MCA. Personally I doubt some of these
>numbers, although I have seen those for MCA in comp.arch.
The quotes numbers for most of the buses mentioned are top end numbers
for bus master to bus slave. Both masters and slaves may go much slower
than shown here.
>First the bus speed/frequency is separate from the CPU clock speed,
>so the clock speed in col 2 is not relevant.
>Second, I have heard in various discussions that...
The clock speed mentioned is, in many cases, a bus clock speed, which
has nothing to do with a CPU clock speed. For example, NuBus always
uses a 10MHz clock, and runs a minimum bus cycle of two clocks. Zorro II
uses a 7.09-7.16MHz clock, and runs a minimum bus cycle of four clocks.
Zorro III doesn't use a clock; the numbers for 16MHz and 25MHz reflect
the speed of the Zorro III bus master defined by the Buster bus controller
designed for the A3000 at various system clock speeds.
>In any case whatever the bus speed may be what matters in the end is
>benchmarked thruput on the job stream of your choice. So far posted
>repeatable head to head comparison benchmark results are sadly lacking
>in the network mcbyc computer wars.
That's essentially my point; folks love to quote maximum theoretical speed,
not actual effective speed or what have you. I suppose if I sat down and
calculated maximum theoretical Zorro III speed, I'd tell you that it maxes
out at 50 MB/s for a standard full cycle, over 150 MB/s for a full burst
cycle. But that's simply based on the specification; I don't expect to be
going that fast in the next year or two, if ever. Real world TTL compatible
parts just don't switch that fast.
>and specifically wrt. the ZORRO III bus
Well, there you go. The CPU to bus interface in the 3000 is pretty close to
the top speed you'll be seeing with the implementation in the 3000. That
says nothing about how fast other bus masters might go, nor how fast a
future Amiga may be able to drive Zorro III.
--
Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests"
{uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy
"I have been given the freedom to do as I see fit" -REM
Kevin Elphinstone (4th Year)
20Mbytes/sec bus speed on an A3000 is not as bad as some of you are making
out it is. I checked the docs I have for MCA on IBM's new toy, the RISC
System 6000, and they claim 20M to 25M sustainable, and up to 40M peak.
But before you're head swells to much, the cache <-> memory speed is
400Mbytes/sec peak. They use a 128 bit bus with two 64 bit memory banks,
with four way interleaving in each bank to give a claimed cycle time of
40nsec.
Pretty amazing stuff.
It seems that for 32 bit buses though, the A3000 stacks up pretty well
Kevin
Darren New
>In <11...@cbmvax.commodore.com>, da...@cbmvax.commodore.com (Dave Haynie)
>|
>|In article <1990May23.0...@uncecs.edu> urj...@uncecs.edu
>|(Rostyk Lewyckyj) writes:
>|>In article <18...@mindlink.UUCP>, a1...@mindlink.UUCP (Harvey Taylor) writes:
>|
>|>Since C= had just changed the bus and added the IBM/PC
>
> Please note that I didn't write any of this >quoted material.
Several people (including Marco) have made this mistake in the past.
Note that the number of '>'s in front of the quote of person X is
always one greater than the number of '>'s in front of the "In article
X said" line. In this case, Lewyckyj said the quoted material and
quoted you within it, but the poster deleted what you said. Actually,
your name should have been taken out to avoid confusion, but it does
not say that you said "Since C= ..." -- Darren
Dave Haynie
>|In article <1990May23.0...@uncecs.edu> urj...@uncecs.edu
>|(Rostyk Lewyckyj) writes:
>|Yeah, I remember that. And what that table doesn't show you is that
>|68030 to NuBus interface on the Mac IIs runs about 5 MB/s.
> How do you know this? I'm not doubting you in particular, I'm just
> looking for an EE101 answer to how to measure &/calculate bus speeds.
Well, I know this mainly because I've seen the figure quoted over and
over again in discussions of the Mac NuBus. But the basic information
on the bus interface is that NuBus is a synchronous bus clocked at 10MHz.
The minimum bus cycle is two 10MHz clocks (20 MB/s), though most devices
run in three clocks (13MB/s). A basic Mac II or IIx runs a 15.8MHz bus,
and must sync up to the NuBus to achieve a transfer. It must take at
least 100ns, worst case, to sync up simply based on the 10MHz clock of
NuBus, though I recall hearing it's more like a worst-case of 150ns.
Once data transfer is acknowledged on the NuBus, this must be translated
into 68030 DSACK. I don't have the NuBus specification handy to be
sure how soon the 68030 can react to data transfer being acknowledged.
In any case, it's the 68030 to NuBus translation that results in the
maximum effective bus speed of NuBus. You rarely have a perfectly
efficient bus translation in any bus converter. Some work quite very
efficiently, others are trouble. In general, the more similar the
two buses are, the better the conversion efficiency. So you might
expect Microchannel to 80386 conversion to work better than 68030
to NuBus conversion, since NuBus looks far less like 68030 bus than
Microchannel resembles 80386.
The other stumbling point is clock conversion. The Mac II, IIx, and
IIci systems each have a main CPU clock that have no relation to the
NuBus clock, so synchronizers much be employed at various points to
avoid any metastabilities in the 68030-to-NuBus cycle conversion state
machine. On the NeXT machine (which apparently runs a CMOS level NuBus
with a 12.5MHz NuBus clock and 25MHz system clock) or a Mac IIfx (which
has a 20MHz local system bus), the bus converter doesn't have to work
out any major asynchronicities, so the CPU to bus interface on either
of these systems has a chance, depending on its implementation, of being
much more efficient.
>|That says nothing about how fast other bus masters might go, nor how fast a
>|future Amiga may be able to drive Zorro III.
> Same questions...
Well, for timing the maximum theoretical speeds for Zorro III full and
multiple cycles, I simply pulled out "The Zorro III Bus Specification by Dave
Haynie", flip to "Chapter 5: Timing", and add up the various lengths of
different cycle events for each type of cycle. That figure sets the minimum
possible cycle time on the bus, in nanoseconds in this case. A cycle
transfers 4 bytes, so if you know ns/byte, it's easy to find bytes/ns,
and ultimately, megabytes/second. Again, actual Zorro III cycle time is
based on the efficiency of the Zorro III bus master and Zorro III bus slave
acting together.
A 68030 isn't a perfect Zorro III bus master, so you'll find that, for a
given memory chip speed, a 68030 will talk to a 68030 memory design faster
than a Zorro III memory design. It'll be harder or more expensive to build
a Zorro III memory board that'll go 20MB/s with a 68030 (I built one, but
it uses expensive SRAM) than it would be to build a native 68030 memory
board that'll go 20MB/s with a 68030. That's rather common on I/O buses,
and a well designed I/O bus master will be able to drive the Zorro III bus
significantly faster than the 68030, or most any CPU, can.
> Harvey Taylor Meta Media Productions
--