>Andrés wrote:
>> Hi VHDL people,
>>
>> is it possible to implement a MOD 12 operation
>> in Hardware ?
>>
>> The Lattice Synthesizer is not able to use any direct implementation.
>>
>> Suggestions are welcome.
>>
>> Best regards
>>
>> Andrés
>
>Something additional:
>
>I am using a counter that counts up.
>
>Every time the counter value mod 12 gets zero I want
>to make a signal 'l_show_burst_complete' HIGH.
>
>I am implementing a back-to-back write for an DDR SDRAM controller.
That's rather different. You should just make a divide by 12 counter,
and reset it at the same time you reset your main counter.
Regards,
Allan
And, to get mod 12 from mod 4 and 3, you use typically "chinese remainder theorem"
or "mixed radix conversion". However, they require multiplications but if you're
lucky those can be done with a few bit shifts. Something to type into Google...
>Hi VHDL people,
>
>is it possible to implement a MOD 12 operation
>in Hardware ?
>
>The Lattice Synthesizer is not able to use any direct implementation.
>
>Suggestions are welcome.
12 = 4 * 3.
Mod 2**N is trivially easy, and mod 2**N-1 is reasonably easy, once
you understand the maths.
This thread describes how to do a mod 3 operation on a 10 bit number
in 1 CLB:
http://groups-beta.google.com/group/comp.arch.fpga/browse_frm/thread/40b7d07440650599/93bef6826d0a16b3
Regards,
Allan
Something additional:
I am using a counter that counts up.
Every time the counter value mod 12 gets zero I want
to make a signal 'l_show_burst_complete' HIGH.
I am implementing a back-to-back write for an DDR SDRAM controller.
Rgds
Andrés