accessing constant in a package
krby_xtrm
----- Package: ---------
package my_data_types is
constant m:integer :=8;
end my_dat_types;
-----------------------
... later in the project
------Project: --------
entity sample is
port(
inp: in std_logic;
outp : out std_logic_vector(m-1 downto 0); -- << here
);
...
is m in '(m-1 downto 0)' is the m in the package..
one more thing, how about if i want to change the value of m in the
package from the project...
sudhi
use work.my_data_types.all;
in your project file.
Runtime changing of port widths may not be supported, if you want to,
say instantiate the above entity with various widths, using GENERIC is
the answer.
-Sudhi
krby_xtrm
--- Package: my_data_types.vhd ----------------------------
library ieee;
use ieee.std_logic_1164.all;
package my_data_types is
constant m:integer :=18;
type my_array is array (natural range<>) of
std_logic_vector(m-1 downto 0);
-----------------------------------------------------------
------Project: --------
entity sample is
port(
inp: in std_logic;
18-bit logic_vector
--------------------
);
...
Like this that my_array would be used in many other projects with
differing 'm', ex. one is 18-bit array, another say, 8-bit array...
how is that?
Jonathan Bromley
<kerby....@gmail.com> wrote:
>right. but if the condition is like this:
>--- Package: my_data_types.vhd ----------------------------
>library ieee;
>use ieee.std_logic_1164.all;
>package my_data_types is
> constant m:integer :=18;
> type my_array is array (natural range<>) of
> std_logic_vector(m-1 downto 0);
>-----------------------------------------------------------
>------Project: --------
>entity sample is
>port(
> inp: in std_logic;
> outp : out my_array(1 to 10); -- << here: 10 array of
>18-bit logic_vector
[...]
>Like this that my_array would be used in many other projects with
>differing 'm', ex. one is 18-bit array, another say, 8-bit array...
>how is that?
It's a well known limitation of VHDL. Packages with generics on them
would be one solution, currently under investigation for VHDL-200x.
There are various possible workarounds, none of them pleasant.
Of course, it's easy to rewrite the package for different projects.
Not elegant, but easy.
The real problems start when you want more than one different
value of "m" in different places in the *same* design.
If you absolutely must have this, consider true 2-dimensional arrays:
package true_2D is
type std_logic_array is
array (natural range <>, natural range <>) of std_logic;
end;
Now it's OK to define
port ( in_a: in std_logic_array(1 to 10, 7 downto 0); ...
But it is quite painful to extract a slice (row) of such an
array. If we assume that the array I just defined is an
array of ten 8-bit bytes, then we can extract one slice
like this...
-- make a subtype that matches second range of in_a
subtype slv_slice is std_logic_vector(in_a'range(2));
-- slice it
function slice(
a: in std_logic_array;
row: in natural
) return std_logic_vector is
variable v: std_logic_vector(a'range(2));
begin
assert row >= a'low(1) and row <= a'high(1);
for i in v'range loop
v(i) := a(row,i);
end loop;
return v;
end;
......
signal my_row: slv_slice;
......
my_row <= slice(a,5); -- gives a(5, 7 downto 0)
Lots of functions and procedures may possibly make this tolerable.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan...@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
krby_xtrm
type true_3D is array (natural range<>) of
std_logic_array(natural range<>, natural range<>);
based on your true_2D array?
one more this, this code is the actual implementation i have to do....
---------
package my_data_types is
constant m: integer :=8;
type my_array is array (natural range<>) of
std_logic_vector(m-1 downto 0);
--------
such that :
----------- PROJECT :-------------------------------
entity demux is
generic ( n : integer := 2);
port(
sel : in integer range 0 to n;
x : in my_array(0 to n); -- array(natural range<>) of
std_logic_vector(m-1 downto 0)
y : out std_logic_vector(m-1 downto 0) -- m is declared in the
package
);
end demux;
....
process(sel)
begin
y <= x(sel); --- here
end process;
...
---------------
that is all i intend to do, a generic demux, that is set only by 'n' in
the project's generic; however in the package the range of 'y' is based
on m....
with the 'true_3d' array above, is that possible?
Jonathan Bromley
wrote:
>i'd been thinking about this lately, is this possible:
>
>type true_3D is array (natural range<>) of
> std_logic_array(natural range<>, natural range<>);
No. When you write
array (.....) of something;
the "something" part MUST be a constrained type, i.e.
its size must be known. Unconstrained ranges are illegal.
On the other hand, the (.....) range can of course be
unconstrained; and it can, if you wish, have more than one
dimension - as in my code fragments.
>one more this, this code is the actual implementation i have to do....
>---------
>package my_data_types is
> constant m: integer :=8;
>
> type my_array is array (natural range<>) of
> std_logic_vector(m-1 downto 0);
>
>--------
This is absolutely fine, since "m" is known at elaboration time.
The problem, of course, is that "m" is then fixed throughout
your design - if you want a different m, you need a different
package.
In many applications, "m" is something fixed throughout the
design - like a bus width - and making it invariant is OK.