Verilog operand sizes
David Jones
1. Is the following legal?
module foo(z);
parameter W=32;
input [W-1:0] z;
wire [31:0] z;
endmodule
This could work if elaborated as-is, but the declaration conflicts for any
other value of the parameter. It is permissible for a Verilog analyzer to
reject this code at parse time (i.e. before elaboration)?
2. Is the following legal?
module bar;
reg [7:0] a;
reg b;
wire [8:0] res = { a + 'b1, b };
endmodule
The issue here is that 'b1 is unsized. It ought to be extended to the size
of integer before being added to a. In this case, one could argue that the
addition is 32-bits wide (assuming integer size=32). Is this sufficient
to make the concatenation kosher, or is the Verilog tool permitted/required to
reject this code on the grounds that the concatenation operands are unsized?
Steven Sharp
>
> input [W-1:0] z;
> wire [31:0] z;
>
> reject this code at parse time (i.e. before elaboration)?
The Verilog language is not as rigorously defined by the LRM as
some other languages (e.g. VHDL). Sometimes you have to look at
common practice in tools to decide what is the best answer.
Verilog-XL doesn't actually check these ranges for matches. It
just uses the range from the net or reg declaration. There may
be designs out there that have been getting away with mismatches.
You have to decide whether you want your analyzer to reject this
design that other tools accept.
> wire [8:0] res = { a + 'b1, b };
Verilog-XL only errors out on the simple case where the operand
is an unsized constant, not an expression containing an unsized
constant or whose width is set by the size of an unsized constant.
Again, you have to decide how picky you want to be. Stephen
Williams can attest to the amount of grief he has gotten from
users over doing tighter checking for this in Icarus Verilog.