XPS behavioral simulation fails: the design is not loaded
ferorcue
After designing a peripheral and checking that it is working with the
BFM simulation, I am trying to simulate the whole system. I created a
simple system with BSB in order to get experience with this
simulation. I generated the Hdl libraries in XPS and modified the
modelsim.ini to use the Smartmodels ( I use Modelsim SE PLUS 6.2a). I
also checked it with:
VSIM>vsim unisim.ppc405 And it is working ok.
XPS creates the directory simulation/behavior with the scripts to
simulate the system in Modelsim. The system was compiled using these
scripts.
I have an error while the system is loaded:
# Loading opb_arbiter_v1_02_e.or_gate(imp)#1
# ** Fatal: (vsim-3348) Port size (1) does not match actual size (32)
for port '/system/opb/opb/opb_abus_i/y'.
# Time: 0 ps Iteration: 0 Instance: /system/opb/opb/opb_abus_i
File: /opt/xilinx/EDK8.2/hw/XilinxProcessorIPLib/pcores/
opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd Line: 125
# FATAL ERROR while loading design
# Error loading design
# 1
I do not how to solve this problem as the opb_arbiter_v1_02_e module
is a Xilinx IP core, and it is read only.
It has to be any solution, because some people are using this kind of
simulation and I am trying to use it with a simple design created with
BSB( bitstream ok, and the software project is the default
TestAppMemory)
Can anyone help me, thanks.
Note: This is almost all the information of Modelsim
# vsim -t ps system_conf
# Loading /opt/modeltech/6.2a/linux/libswiftpli.sl
# Loading /opt/modeltech/6.2a/linux/../std.standard
# Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_1164(body)
...
...
...
# Loading /opt/modeltech/6.2a/linux/libsm.sl
# ** Note (SmartModel):
# Copyright (c) 1984-2007 Synopsys Inc. ALL RIGHTS RESERVED
# ** Note (SmartModel):
# Platform Type: x86_linux (32-bit).
# ** Note (SmartModel):
# You can use the Browser tool to configure the SmartModel
# Library and access information about SmartModels:
# $LMC_HOME/bin/sl_browser
#
# SmartModel product documentation is available here:
# $LMC_HOME/doc/smartmodel/manuals/intro.pdf
# http://www.synopsys.com/products/lm/doc/smartmodel.html
#
# Notice: timing checks disabled with +notimingcheck at compile-time
# ** Warning (SmartModel):
# Model is being requested to run at a finer resolution than
necessary.
# Time: 0 ps Instance:/system/ppc405_0/ppc405_0/ppc405_i/
ippc405_swift/ppc405_swift_inst
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.fpga_startup(fpga_startup_v)
# Loading work.ppc405_1_wrapper(structure)
# ** Warning (SmartModel):
# Model is being requested to run at a finer resolution than
necessary.
# Time: 0 ps Instance:/system/ppc405_1/ppc405_1/ppc405_i/
ippc405_swift/ppc405_swift_inst
# Loading work.jtagppc_0_wrapper(structure)
# Loading jtagppc_cntlr_v2_00_a.jtagppc_cntlr(structure)
...
...
...
# Loading opb_arbiter_v1_02_e.opb_arb_pkg(body)
# Loading opb_v20_v1_10_c.opb_v20(imp)#1
# Loading opb_arbiter_v1_02_e.or_gate(imp)#1
# ** Fatal: (vsim-3348) Port size (1) does not match actual size (32)
for port '/system/opb/opb/opb_abus_i/y'.
# Time: 0 ps Iteration: 0 Instance: /system/opb/opb/opb_abus_i
File: /opt/xilinx/EDK8.2/hw/XilinxProcessorIPLib/pcores/
opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd Line: 125
# FATAL ERROR while loading design
# Error loading design
# 1
Newman
I looked in the or_gate.vhd file and there is a generic that gets
passed in
called C_BUS_WIDTH with a default of 1. Are you setting this value to
what
is required at the upper levels and passing it in? This is a quick
guess on
my part.
Hope this helps,
Newman
ferorcue
yet.
the generic C_BUS_WIDHT has a default of 1, and the upper levels are
using the or_gate.vhd file with the same generic.
What make me angry is that i cannot modify this files, because they
are cores from XILINX, that means that i have not modified them, and
it should work.
I would like to know if someone was able to use the simulation of
designs in Xilinx Platform Studio. And if someone was able to solve my
problem.
Thank you
Mike Treseler
> hello, thank you for answering but i am not able to solve my problem
> yet.
>
> the generic C_BUS_WIDHT has a default of 1, and the upper levels are
> using the or_gate.vhd file with the same generic.
>
> What make me angry is that i cannot modify this files, because they
> are cores from XILINX, that means that i have not modified them, and
> it should work.
The alternative is to enter the design
directly in vhdl or verilog for synthesis.
This way, I still find frustrations,
but I can simulate and edit the code as well
as swear at it :)
-- Mike Treseler
ferorcue
> ferorcuewrote:
I think that I have the solution, I found it in a xilinx webcase.
in system_setup.do change:
"vsim -novopt -t ps system_conf; set xcmds 1;"
Source:
9.1i EDK ModelSim - Error message: "logic.vhd(359): (vopt-1144) Value
0 is out of std.standard.natural range 1 to 32"
04/24/07 11:14:13
Problem Description:
Keywords: optimization, -vopt, -novopt
I am trying to simulate my EDK system. When I run the simulation in
ModelSim 6.2b, I receive an error message similar to the following
during the optimization phase:
"Error Message:
---------------------------------------
D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/hdl/vhdl/
opb_v20.
vhd(550): (vopt-1144) Value 0 is out of std.standard.natural range 1
to
32.
# ** Error:
D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/
park
_lock_logic.vhd(359): (vopt-1144) Value 0 is out of
std.standard.natural
range 1 to 32.
# ** Error:
D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/
park
_lock_logic.vhd(429): (vopt-1144) Value 0 is out of
std.standard.natural
range 1 to 32.
# Optimization failed
# Error loading design
# Error: Error loading design
# Pausing macro execution"
I was able to simulate this same design using a previous version of
ModelSim (for example, 6.0a and 6.2a). The previous version of
ModelSim did not include this optimization phase. What could be the
problem?
Solution 1:
The problem is that in the later version of ModelSim, it is
automatically inserting the -vopt command by default, which clashes
with the EDK IP files for the EDK cores. This command performs global
optimization on Verilog and mixed-HDL designs after they are
compiled,
which is not necessary for the EDK IP models.
You can work around this issue by inserting the -novopt command in
the
"do file" that you are using to run the simulation. Alternatively,
you
can work around this issue by setting the "modelsim.ini" variable
"VoptFlow" to 0 (zero). The "modelsim.ini" files are located in the
c:
\<modelsim>\, c:\<ise_compiled_libraries> and c:
\<edk_compiled_libraries> directories