Simple 8253

[aleksa]

This is what I have in mind:

1. Counter counts to zero, issues an IRQ, and reloads.
2. The CPU gets the IRQ and writes the new 'reload' value,
which should remove the IRQ.

signal counter, reload : STD_LOGIC_VECTOR (15 downto 0);

if falling_edge(clock) then
if counter = 0 then
counter <= reload;
irq <= '1';
else
counter <= counter - 1;
-- irq <= '0'; -- AUTO
EOI
end if;
end if;

if rising_edge(write) then
reload <= dbus; -- reload
value
irq <= '0'; --
acknowledge IRQ, EOI
end if;

If I use one process, webpack is giving me an error:
Multi-source in Unit <test> on signal <irq>; this signal is connected
to multiple drivers

If I use two processes: Signal irq cannot be synthesized.
Something like, irq is bound to two clocks.

AUTO EOI works (in simulation, dont even have the chip yet),
but the clock can be as low as 30Hz, which is too slow.

How should I ACK an IRQ with the CPU?

[Symon]

if write = '1' then
irq <=0;
reload <= dbus;
elsif falling_edge(clock) then

if counter = 0 then
counter <= reload;
irq <= '1';
else
counter <= counter - 1;

irq <= '0'; -- AUTO EOI
end if;
end if;

I know I shouldn't do homework for people but what the hey. Use the write
signal as an asynchronous reset. Also, use numeric.std . It's lovely.

http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

HTH, Syms.

[aleksa]

Yes, it definately helps, thank you!

I'll see about that numeric.std

This isn't homework, I'm learning on my own, more or less from
scratch.
If I was a student, I would say so.

[Symon]

aleksa wrote:
>
> This isn't homework, I'm learning on my own, more or less from
> scratch.
> If I was a student, I would say so.

Please forgive me. Sadly, not all posters here share your honesty of
disclosure.

Good luck with your project, Syms.