Quartus Timing Analyzer question

[Zorjak]

Hi. I am working with Alera Quartus software on FPGA realization of
STFT(Short Time Fourier Transform) and I have one problem. I am
constantly getting this waring

"Warning: Circuit may not operate. Detected 140 non-operational
path(s) clocked by clock "clk" with clock skew larger than data
delay."

Shortly: I create one entity "A", compile it and I don't get this
warning (I dont have that "non-operational paths" in this project),
but when I use this entity for some other project I get this worning
saying me that this "non-operational paths" are in previosly create
"A" entity.
I am not shure that I know what this non-operational paths are.

Could anybody help me about this. Any kind of help would be precious
to me.

Thanks

[dkar...@gmail.com]

Zorjak,

A non-operational path is a "Hold Violation". We give this type of
warning in cases where there is no clock requirements and the clock
delay to the destination/latching register is much larger than the
clock delay to the source/launching register (larger than the data
delay), creating harmful clock skew. This is a problem because the
data travels to the destination register much faster than the clock,
creating a situation where the destination register will latch data
sent by the source register on the "same clock edge" (as oppose to the
following clock cycle). This is very serious as it means the circuit
will never operate no matter what the clock speed is. See
http://en.wikipedia.org/wiki/Clock_skew.

So, why are you seeing this?
This can happen if Quartus cannot place the clock on a global clock
network, or more often, if the design has gated clocks (i.e. logic in
the clock path), or ripple clocks not defined as derived clocks.

The reason why you get the warning in some cases and not in others is
likely plain luck. Based on the fit, the two registers may have
positive clock skew (which result in the hold violation) or negative
skew (which simply results in a lower Fmax). Or the different fit may
simply slow down the data path such that data delay > clock skew. From
the Clock Hold Timing Analyzer report panel, select the row with the
Non-operational message, and use the mouse right-button "List Path"
command to get details on the path. It will show you details on both
the clock skew and data path

>From the warning, I know you are not defining any clock requirement. I
strongly recommend that you create clock requirements for all your
clocks. This should include derived clocks on any ripple clocks (e.g.
clock dividers). This will help the fitter come up with a better
answer. If you go to "Assignments | Settings..." and clock on the
"Fitter Settings", you will also find an "Optimize hold timing" check.
You can change its value to "All Paths" to have the fitter insert
delay to try to avoid hold violations. But this setting will only work
well if you define your clocks correctly (this is very important).
Please look at the following handbook chapter for more on timing
analysis

http://www.altera.com/literature/hb/qts/qts_qii53004.pdf

David Karchmer
Altera Corp

[Zorjak]

Thanks David for this explanation.

I think that I understood you. Thanks for this advices. You are great.

Thanks again

[Zorjak]

When you said "define clock corectly", you meant define them in timing
analyzer. Am I right? I did that and I found which paths have "Hold
Violation". But I don't know what to do now. What should I do to get
rid of this "Non operational path". Should I insert some "delay" in
these datapaths (how?), or there is another way. What can be done in
this situation? Also, I defined all clocks (in timing analyzer), and I
set on "optimaze hold timing" stating "all path", but I still have
these "non operational paths".

I apologize if this questions is so stupid but I realy don't know how
to move on. Any advice is helpfull.

Thanks

[dkar...@gmail.com]

> When you said "define clock corectly", you meant define them in timing
> analyzer. Am I right?

Yes, all clocks need to be correctly defined in the Timing Analyzer

> I did that and I found which paths have "Hold
> Violation". But I don't know what to do now. What should I do to get
> rid of this "Non operational path".

In your case, I would continue focusing on why you have clock skew. A
clean design should not have any clock skew to beging with, so changes
in your HDL will likely be needed. As I said before, try doing a "List
path" operation (use button-2 mouse on Hold Clock panel), and expand
the clock skew message to get the detail path of both the source clock
and the destination clock. You can locate to the chip planner and/or
tech map viewer to visualize the path. Check specifically for
combinational logic in your clock path, and if you find it, try to
change your HDL to get rid of it (e.g. use the register's clock enable
instead on an AND gate in your clock path).

The other thing you want to check is your global clock utilization.
Check the "Global Signals" under the "Resource Section" in the fitter
report and confirm you are not running out of global signals, and that
the clock in question has access to global resources.

Also, take a look at the "Timing Optimization Advisor" and read
http://www.altera.com/literature/hb/qts/qts_qii52005.pdf and
http://www.altera.com/literature/hb/qts/qts_qii5v1_02.pdf for more
ideas.

Good luck.

-David Karchmer
Altera

[Zorjak]

Thanks again, David. You realy helped.

I successed to get rid of this warning but I am still not shure
how:):):). For now its ok, but obviosly | have to learn much more.

Anywhay, this literature you recomended to me was realy helpfull.
Thanks again