XPLA3 coolrunner programming tool?
Didi
from Xilinx so now I can program one of their coolrunners via JTAG
with my
toolchain (the CPLD on this design is reprogrammable over the net,
i.e. the
board CPU does its JTAG access etc.).
I am now getting to what should be the easy part - writing the CPLD
source
to produce some (very simple) logic in a jedec file, after which I am
fine.
I got the current xilinx software, started it under windows and got
really
scared.
Last time I used a not-in-house written logic compiler tool it was
the PHDL
thing for the Philips coolrunner (before I had my tool working). It
was blindingly
obvious how to use it and I don't remember having to discover much if
anything
about it, I just used it. Did not waste an hour.
I already wasted a few hours with the new xilinx tool.
It looks like because I want to hit a nail - and I do know how to use
a hammer quite
well - I have to hire a farm of robots so one will drive another to
the shop
where they will pick a truck of hammers and bring them back for
another
robot to choose the right hammer, then they'l put together a table
onto
which the operation will be performed and eventrually the talk robot
will
be telling me how to proceed with which hammer so I can hit my nail
while
holding my arms to protect me from injuring myself.
Just terrific.
Can someone please suggest something simpler? Which is my fastest way?
I am not interested in learning all about their tools, I just want my
logic
into a jedec file (normally a 10 minutes' task here for what this is
with my
old coolrunner tools, but now I want to use a xcr3128xl part). There
is some
ABEL thing, is it usable in a way similar to more sane CPLD tools? (I
gather
it gets translated into vhdl to be processed but I guess I can live
with that for
now). Or their schematic entry, can it be usable? I wasted an hour
until I
**began to** figure out how to assign pins to things (far from having
mastered
that yet - not bad for a guy who has written his own toolchains for
such stuff
while having to do some reverse enginnering on the way, eh...).
Thanks,
Dimiter
------------------------------------------------------
Dimiter Popoff Transgalactic Instruments
http://www.tgi-sci.com
------------------------------------------------------
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Antti
I wonder :)
why so complicated..
JTAG info for Xilinx devices is PUBLIC (soso 95%) so no need to get it
under NDA
the jedec bitmap info is not so public, but i did RE it withing a few
days :)
as of "doing something"
1) use schematic for design entry
2) use the graphical tool to assign pins
it works, you should get leds blinking withing hours
from there go as want, use VHDL or verilog both work ok
Antti
-jg
> There is some
> ABEL thing, is it usable in a way similar to more sane CPLD tools? (I
> gather it gets translated into vhdl to be processed but I guess I can live
> with that for now).
ABEL is a good tool flow for CPLD, and especially good if you want
to keep close to the JED file.
AFAIK, the Xilinx ABEL flow still works, and as you say, it converts
into spagetti VHDL for the rest of the tool chains, and timing.
Xilinx used to include some .abl source examples - if you search for
.abl, what do you find ?
The fitters can report (.rpt) Boolean Eqns in ABEL format, so you can
correlate that with the source code, and track polarity fuses, and
macrocell config fuses etc.
Those report files also have some fuse-level matrix tables,
that you can use to trace small changes.
What happen in-between you can pretty much ignore :)
Somewhere in the depths, I think the fitters still swallow PLA files/
BLIF formats, and if you are adept at tools, you could even create an
assembler that output BLIF files for the fitters...
A compact Xilinx CPLD flow would be nice to see :)
-jg
Uwe Bonnes
> JTAG info for Xilinx devices is PUBLIC (soso 95%) so no need to get it
> under NDA
There are no 1532 BSDL files in the Xilinx/11.1/ISE/xpla3/data/ directory,
so NDA is probably needed.
...
--
Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Didi
Hi Jim,
thanks for trying to help.
> ...
> Xilinx used to include some .abl source examples - if you search for
> .abl, what do you find ?
Nothing. This in what I downloaded from xilinx' site a month (or was
it a few months) ago. It installed 4-5 separate things, all useless
so far. Impact 11, ISE 11, Plan ahead 11, system generator 11, some
accelDSP 11 thing. No .abl files to be seen.
After a few hours of toying with the schematics tool I could not
make it assign pins - just put a 74161 and wanted it to compile,
no - it wants me to edit the vhdl file to finish, just does not work.
Then I tried to start that "plan ahead" thing - just as useless,
it offers me only FPGA choices. The rest of the applications appear
to be stuff I won't ever need.
I located a CD here I with their webpack 3.2 - it has survived
somehow.
It does get installed and there are 4 .abl files on it - the syntax
looks sane enough. But (on the menus) I can see no way to make it
generate a jedec file, this is probably done by the programmer
part (the second icon it installed) which just does not work,
pollutes the whole screen with "OK" windows in a loop (probably
because it does not find its programmer).
So I seem to be stuck - no Xilinx tool I have managed to locate
so far will do Abel -> jedec. Paying them up to let me do
that is not an option I would even consider.
Can you please suggest something you have used and know it
will work?
Didi
> ....
> So I seem to be stuck - no Xilinx tool I have managed to locate
> so far will do Abel -> jedec.
No longer that. I located on my disk something I had downloaded
some months back while planning this effort - webpack 6.3i., on
someones advice IIRC.
It does seem to compile ABEL files, gets stuck at the end
(with my source only) so far but this is after it generates
the jedec file which is what I am after. Cannot see what it thinks
it has done in the html report (it just does not work, "child process
failed"), but well, this is a step in the right direction.
But I am sure I will have to invest a few weeks into integrating
the xpla3 into my logic compiler, these xilinx tools just
are not usable.
Here is a simple source for a 64 cell coolrunner from the Philips
times: http://tgi-sci.com/misc/mb2ata.txt , I am used to be
able to generate that within < a day...
I will of course still welcome all help, I am still far from
done with this.
-jg
>
> I will of course still welcome all help, I am still far from
> done with this.
>
> Dimiter
>
those and zip the results if you give an email ?
-jg
Didi
Thanks Jim, I'll ask for that if I get stuck again. But for now
I seem to be through, I managed to do some simplest code
(1 toggling bit shifted through 5 others, just what I typed
in without thinking) and lo and behold, this not only made it
through the xilinx tool but got programmed into the part by
my jedec->isp translator and my jtag thing... To my amazement
the correct pins are toggling :-).
Dimiter
P.S. BTW, my email address here ( d...@tgi-sci.com ) is valid,
in case you need it.
-jg
I've blown the dust off the directory(s), and it barfed on converting
the old projects - but it happily made new ones.
* new Project (name becomes subdir)
* right click add source [select .ABL file]
* double click on device, select XCR3128XL
* click on source
* Double click on Fitter report in process list
* Double click on generate Jtag file in process list
and voila, truckloads of files, but the ones that matter are .rpt,
and
.jed
If I right-click on [fit].properties, I can select HDL equation style,
where you can choose Source/ABEL/Verilog/VHDL, and that's what it uses
in the fitter report files. - select the most readable
This is a legacy tool chain, but Xilinx can't have broken any of this,
on newer versions can they ?! ;)
-jg
Antti
sure they can
break any legacy with any minor update of the tools
they can
Antti
-jg
> > This is a legacy tool chain, but Xilinx can't have broken any of this,
> > on newer versions can they ?! ;)
>
> > -jg
>
> sure they can
> break any legacy with any minor update of the tools
> they can
Antti - Did you miss the winky ?? ;)
I've sent Dimiter a disk image of an .ABL project compiled into a
XCR3128, so he can check what has changed....
Who knows, the gods might even smile, and given him the same
answer...?!
-jg
Didi
Thanks Jim, I'll hopefully know more after some sleep (dead tired
now). Why am I getting to sleep at 12 AM is another story, I get
out of sync sometimes and the I get back an hour per day (yesterday
it was 10 AM but today I pushed it some more).
Dimiter
Didi
> I've sent Dimiter a disk image of an .ABL project compiled into a
> XCR3128, so he can check what has changed....
While having my morning coffee at 11 PM (still half full) I tried
the newest version I have here (ISE11) on my test project, the one
with the one toggling bit shifting through another five.
I got a warning that the project would be converted to a new
format not usable by older versions; and a promise the old
version would be zipped somewhere (yet to check that, but I
have the source on my DPS disk beyond any alien access anyway).
The the project got open, but the Abel source was gone; the
top source now was its translation to vhdl. Fair enough, I thought,
I was warned for that sort of thing. What I was not warned of
was the fact that it would no longer work... It just won't
compile, I think it does not preserve the pin numbers I
have assigned in the Abel file.
I suppose it can be tweaked to eventually work, if there
were any sane reason why someone would want to do that.
I don't, that's sure :-).
But I was reminded once more why it is so important
to have all design tools under control, the coolrunner
series is the finest programmable silicon I have seen and
I clearly will have to adapt my lc to the 3 and perhaps
2 series, hopefully they will live for another while.
-jg
> On Nov 11, 11:13 am, -jg <jim.granvi...@gmail.com> wrote:
>
> > ....
> > I've sent Dimiter a disk image of an .ABL project compiled into a
> > XCR3128, so he can check what has changed....
>
> While having my morning coffee at 11 PM (still half full) I tried
> the newest version I have here (ISE11) on my test project, the one
> with the one toggling bit shifting through another five.
> I got a warning that the project would be converted to a new
> format not usable by older versions; and a promise the old
> version would be zipped somewhere (yet to check that, but I
> have the source on my DPS disk beyond any alien access anyway).
> The the project got open, but the Abel source was gone; the
> top source now was its translation to vhdl.
Fair enough, I thought,
> I was warned for that sort of thing.
Err No. I'd say NOT fair-enough.
WHY should they need to replace YOUR source code ?
If they have Abel-to-VHDL working, then simply run that in the
background.
I was told by a friend a couple of years back, that was how Xilinx
handled his abel - it did VHDL spins, but they were 'hidden', and it
took Xilinx a few months to knock the edges off that change, but it
DID sound like it all worked.
> What I was not warned of
> was the fact that it would no longer work... It just won't
> compile, I think it does not preserve the pin numbers I
> have assigned in the Abel file.
> I suppose it can be tweaked to eventually work, if there
> were any sane reason why someone would want to do that.
> I don't, that's sure :-).
> But I was reminded once more why it is so important
> to have all design tools under control, the coolrunner
> series is the finest programmable silicon I have seen and
> I clearly will have to adapt my lc to the 3 and perhaps
> 2 series, hopefully they will live for another while.
Have you looked at the Atmel ATF1508RE ?
I use the CUPL tool flows on their ATF15xx family.
It compiles in a fraction of a second, has a stable, flash-Drivable
image and it can create test vector files.
Hooked to a button in my favourite text editor.
Simple.Stable.Bulletproof (well, almost: Zero Angst)
-jg
Didi
> ...
> I was told by a friend a couple of years back, that was how Xilinx
> handled his abel - it did VHDL spins, but they were 'hidden', and it
> took Xilinx a few months to knock the edges off that change, but it
> DID sound like it all worked.
That is true, it does seem to work. On the 6.3 version, at least.
The end result I get does go through that conversion as well, I
can see that during compilation, the vhdl source is also visible
I think.
What does seem not to work in the 11 thing is some higher level
automation, they don't bother parsing the Abel source for pin
assignments and endup without any (my assumption only, could
be anything else).
Dimiter
------------------------------------------------------
Dimiter Popoff Transgalactic Instruments
http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/
Original message: http://groups.google.com/group/comp.arch.embedded/msg/bc9607aec82349d8?dmode=source
Gabor
I would not consider ISE 11 for anything but the very latest
FPGA's. ISE 6.3 is probably the most stable version and if
your device is included, you should use it.
I have to admit that I use Verilog almost exclusively for
projects since moving away from Foundation 4.1 (the
Aldec-based one) which had decent schematics. I still
have that version running to support old projects, but
I think it may predate the Coolrunner II. In any case
that version certainly had Abel and I used it. It also
had serious bugs including an inability to deal with
paths that are not 8.3 all the way up from the root
and a necessity to have the execution path point to
the Abel compiler even when running from the GUI. The
usual symptom if your file name was longer than 8 characters
was to fail with no explanation given.
Xilinx has already decided to orphan some older FPGA
products with ISE 11. ISE 10.1.03i is the last version
to support the older parts. It is also fairly stable
and you can get the webpack version with a little bit
of browsing (older versions are referred to as "classic").
In any case the GUI for newer tool versions seems to
get less intuitive and more clunky with each version,
as you have no doubt seen. I don't think Xilinx ever
had a version that would allow top-level code in Abel,
but I could be wrong on that because most of my designs
are FPGA based rather than CPLD where top-level Abel
would make sense. If you need to do anything serious
with Coolrunner I'd suggest moving to VHDL or Verilog
just to avoid the crappy schematic editor.
Oh for the days of PALASM...
Regards,
Gabor
-jg
> I don't think Xilinx ever
> had a version that would allow top-level code in Abel,
> but I could be wrong on that because most of my designs
> are FPGA based rather than CPLD where top-level Abel
> would make sense.
The ABEL examples I have here, do not need to have SCH top levels.
( I think one does, to show how it can be done..)
-jg
-jg
>
> That is true, it does seem to work. On the 6.3 version, at least.
> The end result I get does go through that conversion as well, I
> can see that during compilation, the vhdl source is also visible
> I think.
>
> What does seem not to work in the 11 thing is some higher level
> automation, they don't bother parsing the Abel source for pin
> assignments and endup without any (my assumption only, could
> be anything else).
By default I think it auto-fits (floats the pins), but if you click
Lock Pins, you get a .UCF for that fit pass, and can then move the
pins about in that file.
Usually I let the fitter have first pass, and create the reports etc,
and then I start worrying about the pins.
It's also good to get design thru the hoops once, before starting to
nail things down..
Not extracting that info from ABEL is rather lazy of Xilinx - that's
really intern level stuff, perhaps they don't sell that many PLDs into
long design life projects ?
Still, a generated UCF file looks simple enough..
-jg