/* omap3_target.S
 *
 * (c) 2008, Dirk Behme, dirk.behme@gmail.com
 *
 * This small test application is loaded into internal
 * OMAP3 SRAM and there prints blinks with user LEDs and/or
 * prints "Hello OMAP3" to UART3 in infinite loop. I.e. after
 * downloading via OMAP3 serial or USB boot ROM you should be able 
 * see blinking LEDs and/or to switch to terminal  program, e.g.
 * minicom, and there observe above output.
 *
 * ----------------------------------------------------------------------------
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *---------------------------------------------------------------------------*/

/* Pin mux definitions */
#define  DIS	(0 << 3)
#define  EN	(1 << 3)
#define  PTD	(0 << 4)	
#define  IDIS	(0 << 8)
#define  IEN	(1 << 8)
#define  M0	0
#define  M4	4

.text
.globl _start
_start:
	/* If SYS_CLK is being divided by 2, remove for now */
	ldr	r1, PRM_CLKSRC_CTRL
	ldr	r0, [r1]
	orr	r0, r0, #(1 << 6)
	bic	r0, r0, #(1 << 7)
	str	r0, [r1]

	/* Enable I and F Clocks for GPT1 */
	ldr	r1, CM_ICLKEN_WKUP
	ldr	r0, [r1]
	orr	r0, r0, #((1 << 2) | (1 << 0))
	str	r0, [r1]
	ldr	r1, CM_FCLKEN_WKUP
	ldr	r0, [r1]
	orr	r0, r0, #(1 << 0)
	str	r0, [r1]

	/* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset.  WD3
	 * should not be running and does not generate a PRCM reset.
	 */	
	ldr	r1, CM_FCLKEN_WKUP
	ldr	r0, [r1]
	orr	r0, r0, #(1 << 5)
	str	r0, [r1]
	ldr	r1, CM_ICLKEN_WKUP
	ldr	r0, [r1]
	orr	r0, r0, #(1 << 5)
	str	r0, [r1]

	ldr	r1, CM_IDLEST_WKUP
wait1:
	ldr	r0, [r1]
	tst	r0, #(1 << 5)
	beq	wait1		/* wait while bit is zero */
	
	ldr	r1, WD2_BASE
	ldr	r0, WD_UNLOCK1
	str	r0, [r1, #0x48]
	
wait2:
	ldr	r0, [r1, #0x34]
	tst	r0, #0x1F
	bne	wait2		/* wait while bits are not zero */

	ldr	r0, WD_UNLOCK2
	str	r0, [r1, #0x48]

	/* Pin mux */
	ldr	r1, OMAP34XX_CTRL_BASE
	mov	r0, #((IDIS | PTD | DIS | M4)) /* GPIO_149 */
	strh	r0, [r1, #0x7E]
	mov	r0, #((IDIS | PTD | DIS | M4)) /* GPIO_150 */
	strh	r0, [r1, #0x80]
	mov	r0, #((IEN  | PTD | EN  | M0)) /* UART3_CTS_RCTX */
	strh	r0, [r1, #0x9A]
	mov	r0, #((IDIS | PTD | DIS | M0)) /* UART3_RTS_SD */
	strh	r0, [r1, #0x9C]
	mov	r0, #((IEN  | PTD | DIS | M0)) /* UART3_RX_IRRX */
	strh	r0, [r1, #0x9E]
	mov	r0, #((IDIS | PTD | DIS | M0)) /* UART3_TX_IRTX */
	strh	r0, [r1, #0xA0]
	
	/* Enable GPIO5 clocks for blinky LEDs and UART 3 clocks */
	ldr	r1, CM_FCLKEN_PER
	ldr	r0, [r1]
	orr	r0, r0, #((1 << 16) | (1 << 11))
	str	r0, [r1]
	ldr	r1, CM_ICLKEN_PER
	ldr	r0, [r1]
	orr	r0, r0, #((1 << 16) | (1 << 11))
	str	r0, [r1]

	/* Blink LEDs */
	ldr	r1, OMAP34XX_GPIO5_BASE
	mov	r2, #(1 << 21) /* Debug LED 1 */
	mov	r3, #(1 << 22) /* Debug LED 2 */
blink:	
	/* turn LED1 on and LED2 off */
	str	r2, [r1, #0x94]
	str	r3, [r1, #0x90]

	/* delay for a while */
	mov	r4, #1000
	bl	delay

	/* turn LED1 off and LED2 on */
	str	r2, [r1, #0x90]
	str	r3, [r1, #0x94]

	/* delay for a while */
	mov	r4, #1000
	bl	delay

	/* Infinite loop */
	b	blink

	/* Not used at the moment, backup */
uart_out:		
	mov     r0, #'H'
	bl	putc
	mov     r0, #'e'
	bl	putc
	mov     r0, #'l'
	bl	putc
	mov     r0, #'l'
	bl	putc
	mov     r0, #'o'
	bl	putc
	mov     r0, #' '
	bl	putc
	mov     r0, #'O'
	bl	putc
	mov     r0, #'M'
	bl	putc
	mov     r0, #'A'
	bl	putc
	mov     r0, #'P'
	bl	putc
	mov     r0, #'3'
	bl	putc
	mov     r0, #'\r'
	bl	putc
	mov     r0, #'\n'
	bl	putc
	b       uart_out

putc:	ldr	r2,UART3_BASE
putc1:	ldrh	r1,[r2,#0x14]
	tst	r1,#0x20 
	beq	putc1
	strh	r0,[r2]
	mov     pc, lr

delay:
	subs	r4, r4, #1
	bne	delay
	mov     pc, lr

OMAP34XX_CTRL_BASE:	.word 0x48002100
CM_FCLKEN_WKUP:		.word 0x48004c00	
CM_ICLKEN_WKUP:		.word 0x48004c10
CM_IDLEST_WKUP:		.word 0x48004c20
CM_FCLKEN_PER:		.word 0x48005000
CM_ICLKEN_PER:		.word 0x48005010
PRM_CLKSRC_CTRL:	.word 0x48307270
WD2_BASE:		.word 0x48314000	
WD_UNLOCK1:		.word 0xAAAA
WD_UNLOCK2:		.word 0x5555
UART3_BASE:		.word 0x49020000
OMAP34XX_GPIO5_BASE:	.word 0x49056000