From dbe9edd3cf156743c504674962da12265e3434fb Mon Sep 17 00:00:00 2001 From: Manikandan K Pillai Date: Fri, 25 Jul 2008 12:30:38 +0530 Subject: [PATCH] Patch to put in NET support for OMAP3 EVM - DEV_a0393249_OMAP3EVM_NET_PATCH Signed-off-by: Manikandan K Pillai --- board/omap3evm/omap3evm.c | 113 +++++++++++++++++++++++++++++++++++ drivers/net/Makefile | 1 + include/configs/omap3evm.h | 139 ++++++++++++++++++++++++++----------------- net/eth.c | 5 +- net/tftp.c | 2 +- 5 files changed, 203 insertions(+), 57 deletions(-) diff --git a/board/omap3evm/omap3evm.c b/board/omap3evm/omap3evm.c index a4b2dbe..9cd3a14 100644 --- a/board/omap3evm/omap3evm.c +++ b/board/omap3evm/omap3evm.c @@ -49,6 +49,8 @@ extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #define UNLOCK_2 0x00000000 #define UNLOCK_3 0x0000FFFF +static int setup_net_chip(void); + /****************************************************************************** * Routine: delay * Description: spinning delay to use before udelay works @@ -268,6 +270,10 @@ int misc_init_r(void) /* set clksel_tv and clksel_dss1 to DPLL4 clock divided by 1 */ *((uint *) 0x48004E40) = 0x00001001; + +#if defined (CONFIG_CMD_NET) + setup_net_chip(); +#endif return (0); } @@ -387,3 +393,110 @@ void raise(void) void abort(void) { } + + +/****************************************************************************** + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. Pin Muxing for the SMC9118 is initialized + * here. + *****************************************************************************/ +static int setup_net_chip(void) +{ + int i = 0; + + /* Configure GPMC registers */ + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0150)) = 0x00001000; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0154)) = 0x001e1e01; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0158)) = 0x00080300; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x015C)) = 0x1c091c09; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0160)) = 0x04181f1f; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0164)) = 0x00000FCF; + (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0168)) = 0x00000f6c; + + /* Configure PIN MUX registers */ + /* Enable GPMC Pin Mux Registers */ + /* Enable GPMC_CLK Pin in CONTROL_PADCONF_gpmc_ncs7 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xBC)) |= 0x00180000; + /* Enable CS5 Pin in CONTROL_PADCONF_gpmc_ncs5 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) |= 0x00000018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) &= 0xFFFFFFF8; + /* Enable offmode for nwe in CONTROL_PADCONF_GPMC_NWE register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00000F00; + /* En off mode for noe and ale in CONTROL_PADCONF_GPMC_NADV_ALE reg */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC0)) |= 0x0E000E00; + /* Enable gpmc_nbe0_cle in CONTROL_PADCONF_GPMC_NWE register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00180000; + + /* Enable gpmc_nbe1 in CONTROL_PADCONF_GPMC_NBE1 register and + configuring the mux mode to 0 */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) |= 0x00000018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) &= 0xFFFFFFF8; + /* Enable d15 in CONTROL_PADCONF_GPMC_D15 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xAC)) |= 0x00000018; + /* Enable d14 - d13 in CONTROL_PADCONF_GPMC_D13 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA8)) |= 0x00180018; + /* Enable d12 - d11 in CONTROL_PADCONF_GPMC_D11 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA4)) |= 0x00180018; + /* Enable d10 - d9 in CONTROL_PADCONF_GPMC_D9 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA0)) |= 0x00180018; + /* Enable d8 - d7 in CONTROL_PADCONF_GPMC_D7 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x9C)) |= 0x00180018; + /* Enable d6 - d5 in CONTROL_PADCONF_GPMC_D5 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x98)) |= 0x00180018; + /* Enable d4 - d3 in CONTROL_PADCONF_GPMC_D3 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x94)) |= 0x00180018; + /* Enable d2 - d1 in CONTROL_PADCONF_GPMC_D1 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x90)) |= 0x00180018; + /* Enable d0 and a10 in CONTROL_PADCONF_GPMC_a10 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x8C)) |= 0x00180018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x8C)) &= 0xFFFFFFF8; + /* Enable a9 - a8 in CONTROL_PADCONF_GPMC_a8 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x88)) |= 0x00180018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x88)) &= 0xFFF8FFF8; + /* Enable a7 - a6 in CONTROL_PADCONF_GPMC_a6 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x84)) |= 0x00180018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x84)) &= 0xFFF8FFF8; + /* Enable a5 - a4 in CONTROL_PADCONF_GPMC_a4 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x80)) |= 0x00180018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x80)) &= 0xFFF8FFF8; + /* Enable a3 - a2 in CONTROL_PADCONF_GPMC_a2 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x7C)) |= 0x00180018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x7C)) &= 0xFFF8FFF8; + /* Enable a1 - a0 in CONTROL_PADCONF_GPMC_a0 register */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) |= 0x00000018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) &= 0xFFFFFFF8; + +#if defined(CPU_3430_ES1) || defined(CPU_3430_ES2) + /* GPIO 64 configuration in CONTROL_PADCONF_GPMC_WAIT2 + register mux mode is 4. */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000018; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) &= 0xFFFFFFF8; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000004; + + /* Configure GPIO 176 in CONTROL_PADCONF_MCSPI1_CS1 + register for ethernet ISR mux mode is 4 */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00180000; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) &= 0xFFF8FFFF; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00040000; + + /* Enable Clock for GPIO 1-6 module in CM_FCLKEN_PER + and CM_ICLKEN_PER registers */ + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5000)) |= 0x0003E800; + (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5010)) |= 0x0003E800; + + /* Make GPIO 64 as output pin */ + (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x34)) &= ~(0x00000001); + + /* Now send a pulse on the GPIO pin */ + (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) |= 0x00000001; + for (i = 0; i < 99 ; i++); + (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) &= ~(0x00000001); + for (i = 0; i < 99 ; i++); + (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) |= 0x00000001; +#else + printf ("Unknown revision... \n\n"); +#endif + return 0; +} + diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 84be288..00bcf29 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -66,6 +66,7 @@ COBJS-$(CONFIG_ULI526X) += uli526x.o COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o +COBJS-$(CONFIG_DRIVER_SMC911X) += smc911x.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/include/configs/omap3evm.h b/include/configs/omap3evm.h index e808438..bf78644 100644 --- a/include/configs/omap3evm.h +++ b/include/configs/omap3evm.h @@ -48,23 +48,23 @@ #include /* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) #undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 /* * Size of malloc() pool */ -#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) -#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ +#define CFG_ENV_SIZE SZ_128K /* Total Size Environment Sector */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ /* * Hardware drivers @@ -73,24 +73,24 @@ /* * NS16550 Configuration */ -#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ +#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK V_NS16550_CLK +#define CFG_NS16550_REG_SIZE (-4) +#define CFG_NS16550_CLK V_NS16550_CLK /* * select serial console configuration */ -#define CONFIG_CONS_INDEX 1 -#define CFG_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ +#define CONFIG_CONS_INDEX 1 +#define CFG_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_MMC 1 #define CFG_MMC_BASE 0xF0000000 #define CONFIG_DOS_PARTITION 1 @@ -101,8 +101,9 @@ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_ONENAND /* ONENAND support */ #define CONFIG_CMD_AUTOSCRIPT /* autoscript support */ @@ -116,13 +117,18 @@ #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ #define CONFIG_CMD_MISC /* misc functions like sleep etc*/ #define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_NFS /* NFS support */ + #define CFG_NO_FLASH -#define CFG_I2C_SPEED 100 -#define CFG_I2C_SLAVE 1 -#define CFG_I2C_BUS 0 -#define CFG_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CFG_I2C_SPEED 100 +#define CFG_I2C_SLAVE 1 +#define CFG_I2C_BUS 0 +#define CFG_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 /* * Board NAND Info. @@ -131,18 +137,18 @@ #define CFG_NAND_BASE NAND_BASE /* physical address to access nand at CS0 */ #define CFG_NAND_WIDTH_16 -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define SECTORSIZE 512 #define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 #define CFG_NAND_WP #define CONFIG_JFFS2_NAND @@ -150,50 +156,50 @@ #define CONFIG_JFFS2_DEV "nand0" /* start of jffs2 partition */ #define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 partition */ +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ /* Environment information */ -#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTDELAY 10 #define CONFIG_BOOTCOMMAND "onenand read 80200000 280000 400000 ; \ bootm 80200000" -#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 noinitrd \ - root=/dev/mtdblock4 rw rootfstype=jffs2" +#define CONFIG_BOOTARGS "setenv bootargs console=ttyS2,115200n8 noinitrd \ + root=/dev/mtdblock4 rw rootfstype=jffs2" -#define CONFIG_NETMASK 255.255.254.0 -#define CONFIG_IPADDR 128.247.77.90 -#define CONFIG_SERVERIP 128.247.77.158 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_NETMASK 255.255.254.0 +#define CONFIG_IPADDR 128.247.77.90 +#define CONFIG_SERVERIP 128.247.77.158 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ -#define V_PROMPT "OMAP3_EVM # " +#define V_PROMPT "OMAP3_EVM # " #define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT V_PROMPT -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PROMPT V_PROMPT +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ -#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+0x01F00000) /* 31MB */ +#define CFG_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest works on */ +#define CFG_MEMTEST_END (OMAP34XX_SDRC_CS0+0x01F00000) /* 31MB */ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ +#define CFG_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load address */ /* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ -#define V_PVT 7 +#define V_PVT 7 -#define CFG_TIMERBASE OMAP34XX_GPT2 -#define CFG_PVT V_PVT /* 2^(pvt+1) */ -#define CFG_HZ ((V_SCLK)/(2 << CFG_PVT)) +#define CFG_TIMERBASE OMAP34XX_GPT2 +#define CFG_PVT V_PVT /* 2^(pvt+1) */ +#define CFG_HZ ((V_SCLK)/(2 << CFG_PVT)) /*----------------------------------------------------------------------- * Stack sizes @@ -296,4 +302,27 @@ extern unsigned int boot_flash_type; #define NAND_ENABLE_CE(nand) #define NAND_WAIT_READY(nand) udelay(10) + +/*---------------------------------------------------------------------------- + * SMSC9115 Ethernet from SMSC9118 family + * ---------------------------------------------------------------------------- + */ +#if defined (CONFIG_CMD_NET) + +#define CONFIG_DRIVER_SMC911X +#define CONFIG_DRIVER_SMC911X_32_BIT +#define CONFIG_DRIVER_SMC911X_BASE (0x2C000000) + +#endif /* (CONFIG_CMD_NET) */ + +/* + * BOOTP fields + */ + + +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 + #endif /* __CONFIG_H */ diff --git a/net/eth.c b/net/eth.c index 21d1496..254a11d 100644 --- a/net/eth.c +++ b/net/eth.c @@ -611,7 +611,7 @@ extern int emac4xx_miiphy_initialize(bd_t *bis); extern int mcf52x2_miiphy_initialize(bd_t *bis); extern int ns7520_miiphy_initialize(bd_t *bis); extern int dm644x_eth_miiphy_initialize(bd_t *bis); - +extern int eth_init(bd_t *bd); int eth_initialize(bd_t *bis) { @@ -635,6 +635,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_DRIVER_TI_EMAC) dm644x_eth_miiphy_initialize(bis); #endif +#if defined(CONFIG_DRIVER_SMC911X) + eth_init(bis); +#endif return 0; } #endif diff --git a/net/tftp.c b/net/tftp.c index ea8fea2..78b4f85 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -185,7 +185,7 @@ TftpSend (void) pkt += strlen((char *)pkt) + 1; /* try for more effic. blk size */ pkt += sprintf((char *)pkt,"blksize%c%d%c", - 0,TftpBlkSizeOption,0); + 0,TftpBlkSize,0); #ifdef CONFIG_MCAST_TFTP /* Check all preconditions before even trying the option */ if (!ProhibitMcast -- 1.5.6