/* PinMux automatically generated generic format file dump. */


/* register_address(hex)	register_value(hex)	ball_name(string)	register_name(string)	mux_mode0_name(string)	muxed_mode_name(string) */

0x4A003570	0x1000A	D1	CTRL_CORE_PAD_VIN2A_D2	vin2a_d2	eCAP1_in_PWM1_out
0x4A003780	0x5000A	AC4	CTRL_CORE_PAD_MMC3_CMD	mmc3_cmd	eCAP2_in_PWM2_out
0x4A0037A0	0x1000A	AB5	CTRL_CORE_PAD_MMC3_DAT7	mmc3_dat7	eCAP3_in_PWM3_out
0x4A003794	0x5000E	AC8	CTRL_CORE_PAD_MMC3_DAT4	mmc3_dat4	gpio1_22
0x4A003798	0x5000E	AD6	CTRL_CORE_PAD_MMC3_DAT5	mmc3_dat5	gpio1_23
0x4A00379C	0x5000E	AB8	CTRL_CORE_PAD_MMC3_DAT6	mmc3_dat6	gpio1_24
0x4A00378C	0x5000E	AC9	CTRL_CORE_PAD_MMC3_DAT2	mmc3_dat2	gpio7_1
0x4A003790	0x5000E	AC3	CTRL_CORE_PAD_MMC3_DAT3	mmc3_dat3	gpio7_2
0x4A003510	0x5000E	AH4	CTRL_CORE_PAD_VIN1A_D7	vin1a_d7	gpio3_11
0x4A003624	0x5000E	A7	CTRL_CORE_PAD_VOUT1_D18	vout1_d18	gpio8_18
0x4A00358C	0x5000E	E6	CTRL_CORE_PAD_VIN2A_D9	vin2a_d9	gpio4_10
0x4A0036F0	0xD000E	F14	CTRL_CORE_PAD_MCASP1_AXR15	mcasp1_axr15	gpio6_6
0x4A00377C	0x5000E	AD4	CTRL_CORE_PAD_MMC3_CLK	mmc3_clk	gpio6_29
0x4A003784	0x5000E	AC7	CTRL_CORE_PAD_MMC3_DAT0	mmc3_dat0	gpio6_31
0x4A003440	0x50007	R6	CTRL_CORE_PAD_GPMC_A0	gpmc_a0	i2c4_scl
0x4A003444	0x50007	T9	CTRL_CORE_PAD_GPMC_A1	gpmc_a1	i2c4_sda
0x4A0035EC	0x1000A	E9	CTRL_CORE_PAD_VOUT1_D4	vout1_d4	pr1_ecap0_ecap_capin_apwm_o
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A003590	0x1010D	D3	CTRL_CORE_PAD_VIN2A_D10	vin2a_d10	pr1_pru1_gpo7
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A003598	0x1010D	D5	CTRL_CORE_PAD_VIN2A_D12	vin2a_d12	pr1_pru1_gpo9
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A00359C	0x1010D	C2	CTRL_CORE_PAD_VIN2A_D13	vin2a_d13	pr1_pru1_gpo10
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A0035AC	0x1010D	D6	CTRL_CORE_PAD_VIN2A_D17	vin2a_d17	pr1_pru1_gpo14
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A0035B0	0x1010D	C5	CTRL_CORE_PAD_VIN2A_D18	vin2a_d18	pr1_pru1_gpo15
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A0035B8	0x1010D	B3	CTRL_CORE_PAD_VIN2A_D20	vin2a_d20	pr1_pru1_gpo17
/* PR1_PRU1_DIR_OUT_MANUAL */
0x4A0035BC	0x1010D	B4	CTRL_CORE_PAD_VIN2A_D21	vin2a_d21	pr1_pru1_gpo18
/* PR1_PRU1_DIR_IN_MANUAL */
0x4A0035A0	0x5010C	C3	CTRL_CORE_PAD_VIN2A_D14	vin2a_d14	pr1_pru1_gpi11
0x4A0035E4	0x5000A	F10	CTRL_CORE_PAD_VOUT1_D2	vout1_d2	pr1_uart0_rxd
0x4A0035E8	0x1000A	G11	CTRL_CORE_PAD_VOUT1_D3	vout1_d3	pr1_uart0_txd
0x4A003618	0x1000A	C7	CTRL_CORE_PAD_VOUT1_D15	vout1_d15	pr2_ecap0_ecap_capin_apwm_o
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A003694	0x1010D	D18	CTRL_CORE_PAD_XREF_CLK0	xref_clk0	pr2_pru1_gpo5
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A003698	0x1010D	E17	CTRL_CORE_PAD_XREF_CLK1	xref_clk1	pr2_pru1_gpo6
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036B4	0x9010D	G12	CTRL_CORE_PAD_MCASP1_AXR0	mcasp1_axr0	pr2_pru1_gpo8
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036B8	0x9010D	F12	CTRL_CORE_PAD_MCASP1_AXR1	mcasp1_axr1	pr2_pru1_gpo9
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036D4	0x9010D	B12	CTRL_CORE_PAD_MCASP1_AXR8	mcasp1_axr8	pr2_pru1_gpo10
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036D8	0x9010D	A11	CTRL_CORE_PAD_MCASP1_AXR9	mcasp1_axr9	pr2_pru1_gpo11
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036DC	0x9010D	B13	CTRL_CORE_PAD_MCASP1_AXR10	mcasp1_axr10	pr2_pru1_gpo12
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036E0	0x9010D	A12	CTRL_CORE_PAD_MCASP1_AXR11	mcasp1_axr11	pr2_pru1_gpo13
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0036E8	0x9010D	A13	CTRL_CORE_PAD_MCASP1_AXR13	mcasp1_axr13	pr2_pru1_gpo15
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0035DC	0x1010D	F11	CTRL_CORE_PAD_VOUT1_D0	vout1_d0	pr2_pru1_gpo18
/* PR2_PRU1_DIR_OUT_MANUAL2 */
0x4A0035E0	0x1010D	G10	CTRL_CORE_PAD_VOUT1_D1	vout1_d1	pr2_pru1_gpo19
0x4A003610	0x5000A	C6	CTRL_CORE_PAD_VOUT1_D13	vout1_d13	pr2_uart0_rxd
0x4A003614	0x1000A	C8	CTRL_CORE_PAD_VOUT1_D14	vout1_d14	pr2_uart0_txd
0x4A0036EC	0xD000A	G14	CTRL_CORE_PAD_MCASP1_AXR14	mcasp1_axr14	timer11
0x4A0037C0	0x50001	A26	CTRL_CORE_PAD_SPI2_SCLK	spi2_sclk	uart3_rxd
0x4A0037C4	0x90001	B22	CTRL_CORE_PAD_SPI2_D1	spi2_d1	uart3_txd