Advantages of Parallel Hz

Radium

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May 2, 2007, 2:46:36 AM5/2/07

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Hi:

Below is an example of "parallel Hz"

http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif

If each clock signal is 1 Hz, and you have a billion of them,
staggered such that every 1ns part of the CPU can start, and finish,
an instruction - making the effective 'clock rate' 1 GHz.

The benefit of using a billion 1 Hz clock signals to make a clock rate
of 1Ghz is that such a system would not get as hot as system running
one 1 GHz clock signal . While the overall amount of heat generated by
both systems maybe around the same, the system running a billion 1 Hz
clock signals will have less heat per area than the system running one
1 billion Hz clock signal. Hence, the former system is far less
vulnerable to thermal damage than the latter.

Let's say two CPUs of different frequencies have been running at the
same voltages and amperages and for the same amount of time. The CPU
with a higher-frequency will be hotter than the CPU with a lower-
frequency.

In a "parallel Hz" device the bits maybe completely in serial and the
algorithms and tasks maybe totally non-parallelizable. However, the
frequency is still parallel.

The device I am proposing is completely serial except for the clock
rate.

My proposed device is completely serial except for the frequency. It
uses "parallel Hz" but in terms of everything other than frequency, it
is totally serial and non-parallel. Only the clock rate is parallel.

Parallel Hz = a method using N number of 1 Hz clock signals to gain a
clock rate of N Hz.

My design has a clock rate of 4 GHz that is obtained by using 4
billion 1 Hz clock signals. But otherwise, it is completely serial.

This design would go great for any application that cannot be
efficiently parallelized [in terms of bits]. Examples of such are
arithmetics and Boolean logic. Parallel Hz would work for serial-only
problems because the bits are still in serial. Parallel Hz does not
require that the bits be parallel.

There is a significant difference between "parallel Hz" and "parallel
bits".

A parallel printer is an example of a device that uses "parallel
bits". This has nothing to do with "parallel Hz" because both serial
and parallel devices can use parallel Hz.

Thanks,

Radium

Michael A. Terrell

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May 2, 2007, 3:08:15 AM5/2/07

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Radium wrote:
>
> Hi:

Bye:

--
Service to my country? Been there, Done that, and I've got my DD214 to
prove it.
Member of DAV #85.

Michael A. Terrell
Central Florida

Robert Baer

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May 2, 2007, 3:18:18 AM5/2/07

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Radium wrote:

Ya gots your persumptions ronggg.
If each processor drew a microwatt, a billion would draw (and
dissipate) a kilowatt.

David L. Jones

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May 2, 2007, 3:33:15 AM5/2/07

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That's hilarious.

Dave.

Eeyore

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May 2, 2007, 3:39:27 AM5/2/07

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Robert Baer wrote:

> Radium wrote:
>
> > Hi:
> >
> > Below is an example of "parallel Hz"
> >
> > http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif
> >
> > If each clock signal is 1 Hz, and you have a billion of them,
> > staggered such that every 1ns part of the CPU can start, and finish,
> > an instruction - making the effective 'clock rate' 1 GHz.

Hey idiot.

You already asked this one before. It's as stupid as all your other ideas.

Graham

Ken Hagan

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May 2, 2007, 5:34:24 AM5/2/07

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On Wed, 02 May 2007 07:46:36 +0100, Radium <gluc...@gmail.com> wrote:

> If each clock signal is 1 Hz, and you have a billion of them,
> staggered such that every 1ns part of the CPU can start, and finish,
> an instruction - making the effective 'clock rate' 1 GHz.

I note that actually producing a compiler that can exploit an ILP
of 10**9 is left as an exercise for the reader. That would be a 51
on the Knuth scale of difficulty, no?

insert name

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May 2, 2007, 6:27:48 AM5/2/07

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> My design has a clock rate of 4 GHz that is obtained by using 4
> billion 1 Hz clock signals. But otherwise, it is completely serial.

Very Big LOL
Let me guess, you are mentifex in disguise.
http://www.scn.org/~mentifex/
http://en.nothingisreal.com/wiki/The_Arthur_T._Murray/Mentifex_FAQ

Gary Seven

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May 2, 2007, 10:02:09 AM5/2/07

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Radium <gluc...@gmail.com> wrote:
: Hi:

:
: Below is an example of "parallel Hz"

:
<snip rant>

"Sir, there is a multi-legged creature crawling on your shoulder." [Spock,
c.1967]

DaveM

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May 2, 2007, 10:42:28 AM5/2/07

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"Radium" <gluc...@gmail.com> wrote in message
news:1178088396.3...@o5g2000hsb.googlegroups.com...

> Hi:
>
> Below is an example of "parallel Hz"
>
> http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif
>
> If each clock signal is 1 Hz, and you have a billion of them,
> staggered such that every 1ns part of the CPU can start, and finish,
> an instruction - making the effective 'clock rate' 1 GHz.
>

> Thanks,
>
> Radium
>

LMAO!!!!!!!!!! And just how are you going to make a CPU with a billion separate
clock lines going into it, not to mention all the supporting inter-CPU
communication circuits? All those CPU "parts" need to be managed somehow... the
microcode to do that would require gigabytes of memory on the CPU. Heat would
be the least of your worries.

The OP needs to redirect his/her energy to earthbound reality and stop watching
so many StarTrek reruns.

--
Dave M
MasonDG44 at comcast dot net (Just substitute the appropriate characters in the
address)

Life is like a roll of toilet paper; the closer to the end, the faster it goes.

Radium

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May 2, 2007, 11:57:36 AM5/2/07

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On May 2, 3:27 am, insert name <nos...@nospam.org> wrote:

> Very Big LOL
> Let me guess, you are mentifex in disguise.http://www.scn.org/~mentifex/http://en.nothingisreal.com/wiki/The_Arthur_T._Murray/Mentifex_FAQ

Those mentifex devices are massively-parallel. As I said, my "parallel
Hz" design is intended for applications that are serial.

a7yvm1...@netzero.com

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May 2, 2007, 11:59:16 AM5/2/07

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"My design has a clock rate of 4 GHz that is obtained by using 4
billion 1 Hz clock signals. But otherwise, it is completely serial. "

Design? Design? All I see is a MSPAINT squiggle. Get a LED to flash
with a PIC first. It has a 4 level parallel Hz processor inside. This
will save you money, you just need to buy 250 million of them instead
of a billion. Makes the PCB a bit more manageable too.

Radium

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May 2, 2007, 12:16:48 PM5/2/07

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On May 2, 7:42 am, "DaveM" <masondg4...@comcast99.net> wrote:

> All those CPU "parts" need to be managed somehow... the
> microcode to do that would require gigabytes of memory on the CPU.

No microcode necessary. My design is hard-wired.

quotes from http://en.wikipedia.org/wiki/Microcode :

"Each machine instruction (add, shift, move) was implemented directly
with circuitry. This provided fast performance, but as instruction
sets grew more complex, hard-wired instruction sets became more
difficult to design and debug."

I still prefer the "hard-wired instruction sets"

"a bug could often be fixed by replacing a portion of the microprogram
rather than by changes being made to hardware logic and wiring."

But I still prefer the "hardware logic and wiring".

In addition, I like my device to be set to the lowest gear -- i.e. a
max of 1-bit per cycle.

Here are some analogies of gears, CPU clock rate, and RPM :

http://sound-on-sound2.infopop.net/2/OpenTopic?a=tpc&s=215094572&f=351097254&m=101104492
quotes :

"The Mhz of a CPU is like the max rpm of a car engine. It's not the
same thing as power, because a big engine running at moderate rpm can
produce the same power as a smaller engine running at higher rpm."

"Under this analogy, AMD CPUs are about 50% larger than Intel CPUs to
compensate for their lower clock speeds. It's a question of design -
neither approach is intrinsically right or wrong."

"The Athlon XP number is a power (or performance or speed) rating -
it's measuring the rate at which the CPU will execute a program."

"The P4 Ghz number measures only the clock rate of the CPU - i.e just
the max rpm in my analogy. If you compare two otherwise identical CPUs
the power will increase as the GHz increases. For a long time all CPUs
were similar enough to mean that this meant Ghz was also a valid power
rating."

"That's no longer true. A P4 with a 800Mhz FSB and large cache will be
much faster than amother P4 with a slower FSB or smaller cache running
at the same CPU clock speed. An Intel Pentium-M mobile CPU gives about
50% more processor power than a P4, Mhz for Mhz, just like an AMD XP
or Athlon64."

"The advantage of CPU clock cycle is that it's easy measure and easy
to sell - just one number and bigger means better. The disadvantage is
that it's not actually correct."

"The advantage of Performance Ratings is that it does actually tell
you what you need to know; but it's hard to measure and a bit
subjective because actual CPU performance depends on a large numbr of
factors and can vary quite a lot depending on what benchmarks you
happen to use."

http://forums.techguy.org/hardware/542050-uncertainty-principal.html
quotes:

"A better race car analogy would be thinking of GHz as RPM."

"The RPM of an engine is only enough information to give you a
relative idea of it's power output. Engine "X" running at 3,000RPM is
more powerful than the same engine running at 2,000 RPM. Unless you
know lots of other info (number of cylinders, gear ratios, etc) you'll
have no idea if it is as powerful as engine "Y" at 4,000 RPM."

"Back to your CPU - a Core 2 Duo or Athlon 64 does more work per clock
cycle than a Pentium 4, so a Core 2 Duo at 2 GHz may be substantially
more powerful than a Pentium 4 at 3 GHz. This could be related to a 6
cyl car vs a 8 cyl."

Okay, I'll have to admit, I have am a bit obsessed with theoretical
PCs that are as much hardware, chip-based, massively-serial, use
"parallel Hz" [to the highest extent that is mathematically-possible]
and are set to the lowest gear -- and use as little of software and
memory -- as mathematically-possible for a PC to run efficiently.

Eugene Miya

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May 2, 2007, 2:13:07 PM5/2/07

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In article <1178122608.8...@h2g2000hsg.googlegroups.com>,

Radium <gluc...@gmail.com> wrote:
>Okay, I'll have to admit, I have am a bit obsessed with theoretical
>PCs that are as much hardware, chip-based, massively-serial, use
>"parallel Hz" [to the highest extent that is mathematically-possible]
>and are set to the lowest gear -- and use as little of software and
>memory -- as mathematically-possible for a PC to run efficiently.

So, you were this guy who sent me this post to comp.parallel 3 years back?
And let me guess, that you want it to run Windows?

Return-Path: <ne...@google.com>
Path: not-for-mail
From: curious...@yahoo.com (Curious)
Newsgroups: comp.parallel
Subject: Parallel Quartz Clock
Date: 21 Jun 2004 17:14:29 -0700
Organization: http://groups.google.com
Message-ID: <34a4f456.04062...@posting.google.com>

Is it possible to have a processor with 1 billion 1 Hz clocks to make
1 GHz frequency?

This was and is a test case for Spam Assassin in my mail box.

Let us know when YOU reach the stage of using nitric acid.

--comp.parallel moderator
--

ChrisQuayle

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May 2, 2007, 2:13:24 PM5/2/07

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Radium wrote:

>
> Those mentifex devices are massively-parallel. As I said, my "parallel
> Hz" design is intended for applications that are serial.
>

Sounds a great idea, but to clarify, I guess the instruction stream,
which of course wouldn't originate from parallel programming techniques,
languages, or compilers, just utilises simple hardware serial to
parallel converters to dish out intructions to all the cpu's, radially ?.

Amazing that no one has thought of this before...

Chris

--

----------------------
Greenfield Designs Ltd
Electronic and Embedded System Design
Oxford, England
(44) 1865 750 681

Radium

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May 2, 2007, 4:15:16 PM5/2/07

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On May 2, 11:13 am, ChrisQuayle <nos...@devnul.co.uk> wrote:

> Sounds a great idea, but to clarify, I guess the instruction stream,
> which of course wouldn't originate from parallel programming techniques,
> languages, or compilers, just utilises simple hardware serial to
> parallel converters to dish out intructions to all the cpu's, radially ?.

There is no serial-to-parallel [or visa versa] conversion. Why do you
think there would be such a conversion?

>From start to finish, everything is massively-serial [in terms of bits
(much like a serial printer)] but always in parallel Hz. All parts of
the device use parallel Hz but are otherwise completely serial.

Serial bits. Parallel Hz.

Rich Grise

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May 2, 2007, 6:12:36 PM5/2/07

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On Tue, 01 May 2007 23:46:36 -0700, Radium wrote:
> Below is an example of "parallel Hz"
>
> http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif
>

Maybe you should google for "pipelining" - they've been doing that
for decades, just not with such ridiculous requirements.

Good Luck!
Rich

Rich Grise

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May 2, 2007, 6:13:53 PM5/2/07

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Which is called a "pipeline", and they've been doing it for decades.

Cheers!
Rich

Radium

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May 2, 2007, 8:39:20 PM5/2/07

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On May 2, 3:12 pm, Rich Grise <r...@example.net> wrote:

> Maybe you should google for "pipelining"

Okay. According to my research [on google] pipelining doesn't have
much to do with "parallel Hz".

In addition, pipelining uses buffers and has significant latency. Not
something I am found of.

My dream PC does not have any buffers or latency.

My dream PC uses RAM chips -- instead of magnetic discs -- in to store
information. It is entirely chip-based.

This PC is built in such a way that it freshly generates the correct
electric signals ["on the fly"] instead of playing them back from its
ROM chips.

There are sets of instructions stored in ROMs. In the case of most PC,
these instructions load before the CPU "knows" it has a hard drive or
other peripheral devices. However, in my dream PC, those instructions
be generated in real-time instead of storing them.

I am aware that EEPROM is reliable, low power, customizable, reprogram-
able, cheap and proven. But just out of personal preference, my dream
PC is hard-wired in such a way that it does not need any ROM.

Other specs are below. The stuff below also do not need any ROM memory
because they are physically-built to generate the signals which
correspond to the following.

OS: Windows 98SE
Browser: Mozilla Suite 1.8b

No fans, no discs, no moving parts, no ROM [except for the CD/DVD
recording/playing and re-writing].

IOW, my dream PC would work perfectly but would not need any moving
parts, discs, or fans. The "HDD" would consist of silicon RAM chips in
place of disc-platters and electric parts in place of magnetic parts.
No moving parts, no noise, no fans, no magnets, no hazardous heat.

To put it simply, what I am describing is a PC that does not need to
store any information because all of the signal codings for the info
is generated in real-time.

The following is a bad analogy but I'll add it anyway.

PC reading info from memory = sample playback synth playing back its
samples of sounds of an FM synth.

PC generating its signals in real-time = an *actual* FM synth freshly-
generating its tones "on the fly".

Yes, I know, the above is a poor analogy but I couldn't think of
anything better.

Most importantly, though, my dream PC uses parallel-Hz and is
massively-serial!!

John L

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May 2, 2007, 9:04:32 PM5/2/07

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>If each clock signal is 1 Hz, and you have a billion of them,
>staggered such that every 1ns part of the CPU can start, and finish,
>an instruction - making the effective 'clock rate' 1 GHz.

I hear that if you have nine women working in parallel, you can get a
baby in one month, too.

R's,
John

Michael A. Terrell

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May 2, 2007, 9:07:41 PM5/2/07

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On Radium's world they don't even have to all be women.

MooseFET

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May 2, 2007, 10:43:43 PM5/2/07

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On May 1, 11:46 pm, Radium <gluceg...@gmail.com> wrote:
> Hi:
>
> Below is an example of "parallel Hz"
>
> http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif
>
> If each clock signal is 1 Hz, and you have a billion of them,
> staggered such that every 1ns part of the CPU can start, and finish,
> an instruction - making the effective 'clock rate' 1 GHz.

With a billion CPUs, the leakage current would kill you. If you want
real processing speed at low power, you should look at using 3 phase
clocks. There are several advantages to this. You only have to swap
two lines of the 3 phase clock to invert the order. This means that
the processor can back step. It doesn't really make a general purpose
computer but it would be very handy if you were playing jeopardy.

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May 3, 2007, 9:20:30 AM5/3/07

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"Radium" <gluc...@gmail.com> wrote in message

news:1178171548....@y5g2000hsa.googlegroups.com...

Right...like you know the difference.

Don't you EVER get tired of trolling?

Bob M.

MooseFET

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May 3, 2007, 9:56:56 AM5/3/07

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Noboby gives a darn about clock rate. It is work done per Watt-second
that is the real issue. The 3 phase clock is the lowest number that
has an unambiguous order and thus is the lowest power one with the
property of a reversible order. With a single clock or a two phase
one, the forwards order is always assumed. This greatly limits what
the processor is able to do.

Consider a simple case like this:

You have a list of values that you need to fit a curve to. You know
that a program like this:

for I=1 to 10
print F(I)
next I

would print:

1 17 33 105 117 119 67 52 37 23

Given this you can burn a lot of CPU time figuring out exactly what
F(I) is. With a 3 phase clock, you only need the list, the program to
call the F(I) and a copy of the compiler. You simply invert the C and
B clock lines and then look at source code for F(I) to find out what
the function is. A great deal of energy is saved by doing this.

The little lost angel

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May 3, 2007, 2:16:22 PM5/3/07

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On 1 May 2007 23:46:36 -0700, Radium <gluc...@gmail.com> wrote:

>Hi:
>
>Below is an example of "parallel Hz"
>
>http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif

erm, didn't you go through this last year too?

>The benefit of using a billion 1 Hz clock signals to make a clock rate
>of 1Ghz is that such a system would not get as hot as system running
>one 1 GHz clock signal . While the overall amount of heat generated by
>both systems maybe around the same, the system running a billion 1 Hz
>clock signals will have less heat per area than the system running one
>1 billion Hz clock signal. Hence, the former system is far less
>vulnerable to thermal damage than the latter.

Erm, wouldn't this simply be achievable by making a physically bigger
1Ghz chip? A single fast chip is also much more likely to perform
better for the same amount of heat since most general computing
problems are not readily parallelized, at least as far as I understand
it.

>Let's say two CPUs of different frequencies have been running at the
>same voltages and amperages and for the same amount of time. The CPU
>with a higher-frequency will be hotter than the CPU with a lower-
>frequency.

erm, DUH. Quite obviously something like a P4 running at 3Ghz will be
hotter than a P4 running at 2Ghz if both used the same voltage. The P4
3Ghz will also do more work than the P4 2Ghz, so what's your point
here?

>This design would go great for any application that cannot be
>efficiently parallelized [in terms of bits]. Examples of such are
>arithmetics and Boolean logic.

How so? Perhas you can illustrate with an example of 1 single 40x
speed chip versus a 10 1x speed "parallel hz" chip?

As far as I can see it, if my next instruction was waiting for the
result of the preceding boolean logic result, my single 40x chip will
get me to the next result 10x faster than your 4x //Hz chip.

Since you mention the application cannot be efficiently parallelized,
I take it to mean the instructions are highly dependable on each
other's results. Thus the faster each instruction gets finished, the
faster the next can go.

Not much point having 3,999,999 //Hz units waiting 1sec for the result
of one instruction compared to a 4Ghz chip that could spit out the
next 1million instructions within the same time.

But of course I hardly qualify as a chip architect so feel free to
point out where I'm mistaken :P

--
A Lost Angel, fallen from heaven
Lost in dreams, Lost in aspirations,
Lost to the world, Lost to myself

The little lost angel

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May 3, 2007, 2:20:35 PM5/3/07

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On 2 May 2007 17:39:20 -0700, Radium <gluc...@gmail.com> wrote:

>This PC is built in such a way that it freshly generates the correct
>electric signals ["on the fly"] instead of playing them back from its
>ROM chips.

And how does it know how to generate the correct signals?

>There are sets of instructions stored in ROMs. In the case of most PC,
>these instructions load before the CPU "knows" it has a hard drive or
>other peripheral devices. However, in my dream PC, those instructions
>be generated in real-time instead of storing them.

Isn't it more efficient to calculate static results beforehand and
store them for use, than to waste time generating the same
instructions all the time?

>Other specs are below. The stuff below also do not need any ROM memory
>because they are physically-built to generate the signals which
>correspond to the following.
>
>OS: Windows 98SE
>Browser: Mozilla Suite 1.8b

In other words, your system is not upgradable and has to live with
whatever bugs there are for the entire "useful" life of the system
since everything's hardwired?

>To put it simply, what I am describing is a PC that does not need to
>store any information because all of the signal codings for the info
>is generated in real-time.

A PC that does not store any information... what good is it for?

>Most importantly, though, my dream PC uses parallel-Hz and is
>massively-serial!!

And so ?

kony

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May 3, 2007, 2:29:40 PM5/3/07

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On Thu, 03 May 2007 18:16:22 GMT,
a?n?g?e?l...@lovergirl.lrigrevol.moc.com (The little lost
angel) wrote:

>On 1 May 2007 23:46:36 -0700, Radium <gluc...@gmail.com> wrote:
>
>>Hi:
>>
>>Below is an example of "parallel Hz"
>>
>>http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif
>
>erm, didn't you go through this last year too?
>

Yes this thread is doubly silly.

Robert Redelmeier

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May 3, 2007, 5:01:41 PM5/3/07

to

In comp.sys.ibm.pc.hardware.chips The little lost angel <a?n?g?e?l...@lovergirl.lrigrevol.moc.com> wrote in part:

> A PC that does not store any information... what good is it for?

Not that I wish to support the OP in any way, but a stateless
PC is a terminal, now AKA "Thin Client" or "Internet Appliance".
Information is stored on a server elsewhere, accessible everywhere.

I like Xterminals, but I'm a dinosaur and remember the Real
Thing: terminals that did X and you could log into the networked
machine[s]. Sort of like a VT220 doing graphics. They ran BOOTP
(iso DHCP) and TFTP to boot.

Now you'd want boot from flash and DHCP. The minicomp would be
a small box like a SohO router with SVGA out (only 2D required),
10/100baseT or wireless, a wall-wart for power, and USB or PS/2
for kbd/mse. Very tidy, very neat and very cheap. Add monitor,
kbd, mouse and network to run.

Hardware specs very similar to a SoHo router:
486-class CPU, 64 MB RAM, 64 MB FLASH. Tight Linux SW.

Onboard SSH would be a must, but a key design decision would be
whether to incorporate a browser client to the local X server. Doing
so would usually improve performance and always cut X-traffic. But
this would jeopardize making the box a stateless appliance. That
might depend on whether the box was tethered to a LAN server, or
expected to work standalone.

With software, you can do much the same thing to much more powerful
desktop and laptop machines using something like a Knoppix boot CD.

-- Robert

Radium

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May 3, 2007, 7:28:30 PM5/3/07

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On May 3, 11:20 am, a?n?g?...@lovergirl.lrigrevol.moc.com (The little
lost angel) wrote:

> On 2 May 2007 17:39:20 -0700, Radium <gluceg...@gmail.com> wrote:

> >This PC is built in such a way that it freshly generates the correct
> >electric signals ["on the fly"] instead of playing them back from its
> >ROM chips.
>
> And how does it know how to generate the correct signals?

It's built that way.

How does SB16's FM synth "know" how to generate its FM signals? Much
in the same way.

> >There are sets of instructions stored in ROMs. In the case of most PC,
> >these instructions load before the CPU "knows" it has a hard drive or
> >other peripheral devices. However, in my dream PC, those instructions
> >be generated in real-time instead of storing them.

> Isn't it more efficient to calculate static results beforehand and
> store them for use, than to waste time generating the same
> instructions all the time?

Yes. However, due to my personal opinions, I prefer to use the least
amount of non-RAM storage/memory necessary.

> >Other specs are below. The stuff below also do not need any ROM memory
> >because they are physically-built to generate the signals which
> >correspond to the following.
>
> >OS: Windows 98SE
> >Browser: Mozilla Suite 1.8b

> In other words, your system is not upgradable and has to live with
> whatever bugs there are for the entire "useful" life of the system
> since everything's hardwired?

Well, the system could be made without bugs. Right?

Moreover, upgrades are possible and stored in the RAM chips I
described above.

Now, if those chips had their info erased [like formatting an HDD],
then the upgrades would have to be performed again -- which is an easy
task.

> >To put it simply, what I am describing is a PC that does not need to
> >store any information because all of the signal codings for the info
> >is generated in real-time.

> A PC that does not store any information... what good is it for?

It does store info in the RAM chips.

> >Most importantly, though, my dream PC uses parallel-Hz and is
> >massively-serial!!

> And so ?

My point is, parallel-Hz and "parallel bits" are not to be confused
with each other.

Gavin Scott

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May 3, 2007, 7:36:59 PM5/3/07

to

In comp.arch Robert Redelmeier <red...@ev1.net.invalid> wrote:
> In comp.sys.ibm.pc.hardware.chips The little lost angel <a?n?g?e?l...@lovergirl.lrigrevol.moc.com> wrote in part:
> > A PC that does not store any information... what good is it for?

> Not that I wish to support the OP in any way, but a stateless
> PC is a terminal, now AKA "Thin Client" or "Internet Appliance".
> Information is stored on a server elsewhere, accessible everywhere.

> With software, you can do much the same thing to much more powerful

> desktop and laptop machines using something like a Knoppix boot CD.

And such an "Internet Terminal" system can be ideal for one's parents
or kids, or anyone else who wants a fool-proof easy-to-use computer
setup.

These days not only is the web almost the only application on the
Internet, but it's almost the only computing application. Give
someone a slightly older PC with no hard drive and a Knoppix or
Ubunto live Linux CD and they may be able to accomplish everything
they want to do through a web browser with no local persistent
store of any kind.

Something like Google's web application suite (gmail etc.) would
even let you do normal office application functions as well.

User gets confused? Makes a mistake? Gets a trojan/virus? Just
power cycle the box and the problem is gone. If it fails to boot
to the user's familliar starting state then it's a hardware problem.

"Push the reset button and try again" may be all the tech support
the user ever needs (though this training may turn out to be ill-
advised if you ever let them near a "real" computer :)

G.

Roger_Nickel

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May 3, 2007, 7:58:13 PM5/3/07

to

http://www.ltsp.org/
Linux terminal server project. Seems like a step backwards but certainly
solves many of the usual support problems. Etherboot or Intel PXE for the
terminals is a possibility if the hardware supports it or could boot off
a usb disk or flash card.

Radium

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May 3, 2007, 9:21:06 PM5/3/07

to

Note: I already posted my response to the message below. However,
Google -- being the sick@$$ piece of f--k they are -- did not display
it.

On May 3, 11:16 am, a?n?g?...@lovergirl.lrigrevol.moc.com (The little
lost angel) wrote:

> On 1 May 2007 23:46:36 -0700, Radium <gluceg...@gmail.com> wrote:

> >The benefit of using a billion 1 Hz clock signals to make a clock rate
> >of 1Ghz is that such a system would not get as hot as system running
> >one 1 GHz clock signal . While the overall amount of heat generated by
> >both systems maybe around the same, the system running a billion 1 Hz
> >clock signals will have less heat per area than the system running one
> >1 billion Hz clock signal. Hence, the former system is far less
> >vulnerable to thermal damage than the latter.

> Erm, wouldn't this simply be achievable by making a physically bigger
> 1Ghz chip? A single fast chip is also much more likely to perform
> better for the same amount of heat since most general computing
> problems are not readily parallelized, at least as far as I understand
> it.

Whether the computation is parallelized or not is irreverent.

> >Let's say two CPUs of different frequencies have been running at the
> >same voltages and amperages and for the same amount of time. The CPU
> >with a higher-frequency will be hotter than the CPU with a lower-
> >frequency.

> erm, DUH. Quite obviously something like a P4 running at 3Ghz will be
> hotter than a P4 running at 2Ghz if both used the same voltage. The P4
> 3Ghz will also do more work than the P4 2Ghz, so what's your point
> here?

My parallel-Hz is an efficient means of keeping high-frequency serial
processors cool without needing any cooling equipment.

> >This design would go great for any application that cannot be
> >efficiently parallelized [in terms of bits]. Examples of such are
> >arithmetics and Boolean logic.

> How so? Perhas you can illustrate with an example of 1 single 40x
> speed chip versus a 10 1x speed "parallel hz" chip?
>
> As far as I can see it, if my next instruction was waiting for the
> result of the preceding boolean logic result, my single 40x chip will
> get me to the next result 10x faster than your 4x //Hz chip.

Your 40x chip maybe faster but it runs a significant risk of
overheating unless cooled by a fan.

> Since you mention the application cannot be efficiently parallelized,
> I take it to mean the instructions are highly dependable on each
> other's results. Thus the faster each instruction gets finished, the
> faster the next can go.

Sometimes yes. Sometimes no. In any case, the purpose of parallel-Hz
is to allow serial processors to operate at super-high frequencies
without needing any cooling equipment. Parallel processors [using 1
bit per line] don't need to use parallel-Hz because they don't get as
hot at the same frequencies that would fry a serial processor. This is
partly due to the fact that parallel processors don't have as many bit
transitions as serial processors.

> Not much point having 3,999,999 //Hz units waiting 1sec for the result
> of one instruction compared to a 4Ghz chip that could spit out the
> next 1million instructions within the same time.

Well, if you want a massively-serial PC running at super-high clock
rates and at the lowest gear [1 bit per cycle] without fans, then not
using parallel-Hz can mean disaster for that PC as the high-frequency
signals vaporize the circuits.

Once again, I will point out that there is a significant different
between parallel-bits and "parallel Hz".

A parallel processor uses parallel-bits. A serial processor doesn't.
"Parallel Hz", OTOH, can be used on both serial as well as parallel
processors. However, parallel-Hz doesn't provide any benefit for
parallel processors. For serial processors, parallel-Hz prevents
dangerous increases in temperature that result from high-frequency
signals.

Donald

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May 3, 2007, 9:29:49 PM5/3/07

to

Radium wrote:
>
>
> My parallel-Hz is an efficient means of keeping high-frequency serial
> processors cool without needing any cooling equipment.
>
>

I am sorry, but I missed the beginning of this thread and Its no longer
on my server.

But, If this is your "parallel-Hz" design, why not just patent it and
have the market decide if its any good ??

It seems you are either preaching to the choir or it doesn't really work.

I am not trying to shoot down your ideas, I just don't see anyone doing
a real design with this idea.

donald

kony

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May 4, 2007, 3:50:51 AM5/4/07

to

On Thu, 03 May 2007 19:29:49 -0600, Donald
<Don...@dontdoithere.com> wrote:

>I am not trying to shoot down your ideas, I just don't see anyone doing
>a real design with this idea.
>
>donald

You have realized the crux of the problem. Radium ignores
purpose, that any thought would need a useful gain to be
more than a wasteful folly.

Radium could have followed through with some research and
pitching these ideas to those who have an ability to
seriously contemplate, and possibly implement the ideas, but
instead is only wasting everyone's time with a random
thought then proclaiming "why don't we do this" as if
rejecting modern technology, finding it a problem that needs
resolved, but wouldn't be when technology allowed, was a
reasonable use of time.

Radium lacks a method to achieve any goals, just random
thoughts which more than anything, demonstrate an inability
to use contemporary technology as well as everyone else.
Anyone could claim "oh but what if this or that was better
than it is", but those who actually drive innovation and
progress, do so leveraging the tech that IS available to do
so instead of only finding fault in it.

The funny part is when basic concepts ARE already possible
today, anyone with a thick enough wallet can build a system
without fans or mechanical hard drives. Radiun pitches
this as if it is some new thought but without the key
details of implementation others already follow, if/when
they find it a reasonable alternative, which isn't very
often because when all is said and done, mechanical failures
are managable and can be planned for, and beyond hard
drives, can be, through competent system design, assumed to
be outside the viable lifespan of the system.

Unfortunately, everyone and their brother fancies themselves
to be competent system integrators, but when it comes down
to finer details, suddenly cost often matters more than
lifespan, then only LATER does one claim "it's a problem".
The problem was usually following time-tested strategies
instead of seeing a fault and making random theories instead
of comparing how the system(s) with faults deviated from
those that didn't have same faults.

It is a wilderness out there, plenty of shady businesses
selling parts in the computer biz that are not suitable for
longer term use. Experience and discrimination, not random
rejection of contemorary tech, allows most people to find a
happy medium, but Radium has yet to find that medium and
instead of accepting that Radium has more to learn, Radium
instead drifts off on tangents which are essentially excuses
for why Radium can't manage to use contemporary tech.

jasen

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May 4, 2007, 5:09:38 AM5/4/07

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On 2007-05-03, MooseFET <kens...@rahul.net> wrote:
>
> Given this you can burn a lot of CPU time figuring out exactly what
> F(I) is. With a 3 phase clock, you only need the list, the program to
> call the F(I) and a copy of the compiler. You simply invert the C and
> B clock lines and then look at source code for F(I) to find out what
> the function is. A great deal of energy is saved by doing this.

LOL!

maybe that'd be possible ifthe computer only did reversible operations,
but a computer like that is either useless or trivial.

What you propose is like trying to run a printer in reverse to recycle
paper.

Bye.
Jasen

inv...@example.com

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May 4, 2007, 9:50:03 AM5/4/07

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Radium wrote:

>This PC is built in such a way that it freshly generates the correct
>electric signals ["on the fly"] instead of playing them back from its
>ROM chips.
>
>There are sets of instructions stored in ROMs. In the case of most PC,
>these instructions load before the CPU "knows" it has a hard drive or
>other peripheral devices. However, in my dream PC, those instructions
>be generated in real-time instead of storing them.
>

>To put it simply, what I am describing is a PC that does not need to
>store any information because all of the signal codings for the info
>is generated in real-time.

Generated from what? Pixie dust?

Please explain *in detail* how the first three such instructions
are generated.

MooseFET

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May 4, 2007, 10:39:38 AM5/4/07

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On May 4, 2:09 am, jasen <j...@free.net.nz> wrote:

Darn! Before I even got the patent written, someone else thinks of
it.

MooseFET

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May 4, 2007, 10:50:03 AM5/4/07

to

On May 4, 12:50 am, kony <s...@spam.com> wrote:
[....]

> The funny part is when basic concepts ARE already possible
> today, anyone with a thick enough wallet can build a system
> without fans or mechanical hard drives.

My ZX-81 had neither and booted way faster than any Windoze machine
does.

These days, a few gig of FLASH is well with the budget. A µPD448012
RAM or two would give enough memory to run reasonable applications.
Today, a "PC" could be made that needed no fan or disks and was low
cost. It could do everything most users need a PC to do. It could
come preinstalled with FreeCell, a Web browser, some email program and
an image of the blue screen of death. That last one is to ensure that
most users never realize that this isn't a full up PC running Windows.

The little lost angel

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May 4, 2007, 11:41:19 AM5/4/07

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On 3 May 2007 16:28:30 -0700, Radium <gluc...@gmail.com> wrote:

>On May 3, 11:20 am, a?n?g?...@lovergirl.lrigrevol.moc.com (The little
>lost angel) wrote:
>
>> On 2 May 2007 17:39:20 -0700, Radium <gluceg...@gmail.com> wrote:
>
>> >This PC is built in such a way that it freshly generates the correct
>> >electric signals ["on the fly"] instead of playing them back from its
>> >ROM chips.
>>
>> And how does it know how to generate the correct signals?
>
>It's built that way.
>
>How does SB16's FM synth "know" how to generate its FM signals? Much
>in the same way.

So in other words, your machine that does not store data will now have
to store data about instruments?

>> In other words, your system is not upgradable and has to live with
>> whatever bugs there are for the entire "useful" life of the system
>> since everything's hardwired?
>
>Well, the system could be made without bugs. Right?

Well, if you truly believe in that, then I would have to say you're
delusional :P

>Moreover, upgrades are possible and stored in the RAM chips I
>described above.

So again tihs PC that does not need to store any information has to
store upgrades information.

>> >To put it simply, what I am describing is a PC that does not need to
>> >store any information because all of the signal codings for the info
>> >is generated in real-time.
>
>> A PC that does not store any information... what good is it for?
>
>It does store info in the RAM chips.

But you said it doesn't need to store any information. :P

>My point is, parallel-Hz and "parallel bits" are not to be confused
>with each other.

Ok then what's the practical implication/advantage/whatever of what
you're proposing?

Anthony Fremont

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May 4, 2007, 12:16:26 PM5/4/07

to

The little lost angel wrote:

> Ok then what's the practical implication/advantage/whatever of what
> you're proposing?

There is none. YHBT His posts are even blocked from appearing on
Supernews. They didn't used to be, that was until the flood anyway.
Hmmmmmmm........

Radium

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May 4, 2007, 6:40:19 PM5/4/07

to

> Radium wrote:

Digital electrical generators. Similar to hardware digital tone
generators except it produces digital electric signals corresponding
to data other than tones. It's a hard-wired PC. Read the Wiki-quotes
and my responses to them.

quotes from http://en.wikipedia.org/wiki/Microcode :

"Each machine instruction (add, shift, move) was implemented directly
with circuitry. This provided fast performance, but as instruction
sets grew more complex, hard-wired instruction sets became more
difficult to design and debug."

I still prefer the "hard-wired instruction sets"

"a bug could often be fixed by replacing a portion of the microprogram
rather than by changes being made to hardware logic and wiring."

But I still prefer the "hardware logic and wiring".

Radium

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May 4, 2007, 6:54:51 PM5/4/07

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On May 4, 8:41 am, a?n?g?...@lovergirl.lrigrevol.moc.com (The little
lost angel) wrote:

> On 3 May 2007 16:28:30 -0700, Radium <gluceg...@gmail.com> wrote:

> >On May 3, 11:20 am, a?n?g?...@lovergirl.lrigrevol.moc.com (The little
> >lost angel) wrote:

> >> On 2 May 2007 17:39:20 -0700, Radium <gluceg...@gmail.com> wrote:

> >> >This PC is built in such a way that it freshly generates the correct
> >> >electric signals ["on the fly"] instead of playing them back from its
> >> >ROM chips.

> >> And how does it know how to generate the correct signals?

> >It's built that way.

> >How does SB16's FM synth "know" how to generate its FM signals? Much
> >in the same way.

> So in other words, your machine that does not store data will now have
> to store data about instruments?

No.

> >> In other words, your system is not upgradable and has to live with
> >> whatever bugs there are for the entire "useful" life of the system
> >> since everything's hardwired?

> >Well, the system could be made without bugs. Right?

> Well, if you truly believe in that, then I would have to say you're
> delusional :P
>
> >Moreover, upgrades are possible and stored in the RAM chips I
> >described above.

> So again tihs PC that does not need to store any information has to
> store upgrades information.

Yes, it stores info in the form of RAM. It does not need ROM, though.

However, my dream PC does have the ability to write/read ROM in the
form of optical discs [e.g. CDs/DVDs].

> >> >To put it simply, what I am describing is a PC that does not need to
> >> >store any information because all of the signal codings for the info
> >> >is generated in real-time.
>
> >> A PC that does not store any information... what good is it for?
>
> >It does store info in the RAM chips.
>
> But you said it doesn't need to store any information. :P

Sorry. I meant to say, it does not store any ROM [except for optical
discs].

What would normally be stored in ROM, my PC generates in real-time.

The RAM chips store what would normally be stored in the magnetic
platters of an HDD.

> >My point is, parallel-Hz and "parallel bits" are not to be confused
> >with each other.
>
> Ok then what's the practical implication/advantage/whatever of what
> you're proposing?

As I said before, parallel-Hz allows massively-serial devices to
operate at extremely high clock rates without needing any cooling
equipment.

Bob Myers

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May 4, 2007, 8:32:26 PM5/4/07

to

"Radium" <gluc...@gmail.com> wrote in message

news:1178319291.2...@q75g2000hsh.googlegroups.com...

> As I said before, parallel-Hz allows massively-serial devices to
> operate at extremely high clock rates without needing any cooling
> equipment.

Yes, you've SAID that before, but you have yet to give
any indication at all that it means anything. As usual,
you not only have no clue, you're running a significant
deficit....

Bob M.

Radium

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May 4, 2007, 8:45:56 PM5/4/07

to

On May 4, 5:32 pm, "Bob Myers" <nospample...@address.invalid> wrote:

unread,

May 4, 2007, 10:41:25 PM5/4/07

to

"Radium" <gluc...@gmail.com> wrote in message

news:1178332344.7...@e65g2000hsc.googlegroups.com...

> On May 4, 7:09 pm, "Bob Myers" <nospample...@address.invalid> wrote:
>
>> Just your usual talent at expressing yourself, I guess.
>
> So you don't think it's important to keep circuits from overheating?

Sure it is. But you clearly don't have a clue about how
to do that.

I do realize that you're a troll - I would just like you to consider
becoming a more amusing one.

Bob M.

Donald

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May 4, 2007, 10:42:14 PM5/4/07

to

Why aren't you laughing all the way to the bank ??

You have nothing,

good bye

Radium

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May 5, 2007, 12:47:00 AM5/5/07

to

On May 4, 7:41 pm, "Bob Myers" <nospample...@address.invalid> wrote:

> "Radium" <gluceg...@gmail.com> wrote in message

:
> news:1178332344.7...@e65g2000hsc.googlegroups.com...
>
> > On May 4, 7:09 pm, "Bob Myers" <nospample...@address.invalid> wrote:
>
> >> Just your usual talent at expressing yourself, I guess.

> > So you don't think it's important to keep circuits from overheating?

> Sure it is. But you clearly don't have a clue about how
> to do that.

Use parallel-Hz. Simple.

No offense but I would appreciate serious responses to my questions.
Please leave out the dark humor.

Don Bowey

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May 5, 2007, 1:22:05 AM5/5/07

to

On 5/4/07 9:47 PM, in article
1178340420....@h2g2000hsg.googlegroups.com, "Radium"
<gluc...@gmail.com> wrote:

> On May 4, 7:41 pm, "Bob Myers" <nospample...@address.invalid> wrote:
>
>> "Radium" <gluceg...@gmail.com> wrote in message
> :
>> news:1178332344.7...@e65g2000hsc.googlegroups.com...
>>
>>> On May 4, 7:09 pm, "Bob Myers" <nospample...@address.invalid> wrote:
>>
>>>> Just your usual talent at expressing yourself, I guess.
>
>>> So you don't think it's important to keep circuits from overheating?
>
>> Sure it is. But you clearly don't have a clue about how
>> to do that.
>
> Use parallel-Hz. Simple.

How do you plan to use the 1 Hz. Clock pulses? Just give us an example of
HOW you will use a few of the one pps clock lines to achieve anything useful
at a rate exceeding one pps.

>
> No offense but I would appreciate serious responses to my questions.
> Please leave out the dark humor.
>

You aren't a serious enough troll.

MooseFET

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May 5, 2007, 2:18:59 AM5/5/07

to

FYI: 1 billion processors all losing 1mW is still 1KW ow power being
turned into heat. As you have already been told, the leakage current
alone will destroy your system. Your idea doesn't work.

unread,

May 5, 2007, 9:22:23 AM5/5/07

to

"Radium" <gluc...@gmail.com> wrote in message

news:1178348645.4...@w5g2000hsg.googlegroups.com...

You still don't get it, do you?
Show the physical layout of the clocking circuit on a PCB. You're suggesting
that you can build a computer having a BILLION individual clock lines, each
running at 1pps?? That's just for 1GHz... How many clock lines does that
figure out to be if you wanted to speed up the computer to 4GHz?

LMAOOOOOOOOOOOOOOOO!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

--
Dave M
MasonDG44 at comcast dot net (Just substitute the appropriate characters in the
address)

Life is like a roll of toilet paper; the closer to the end, the faster it goes.

Guy Macon

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May 5, 2007, 10:21:20 AM5/5/07

to

Radium wrote:

>
>MooseFET wrote:
>
>> FYI: 1 billion processors all losing 1mW is still 1KW ow power being
>> turned into heat. As you have already been told, the leakage current
>> alone will destroy your system.
>
>Couldn't circuitry be designed in such a way that the leakage current
>will travel in a path out of the system, instead of toward vital
>circuits?

This troll was clearly compiled with inferior tools.
My guess is that it was created with Visual Troll++
and the Troll Foundation Class, or possibly TurboTroll
2000.

These trolling tools are quite limited, and there is
a severe garbage-collection related performance hit
when you try to optimizing the output of VT++ for
kook-trolling.

IMO, you will get better results using GTC; the Gnu
Troller Collection. GTC is the gold standard for
creating trolls. It is also open Source, fully
reentrant, and compliant with the Triple Troll,
Troll-On-Troll and YATC protocols.

--
Guy Macon
<http://www.guymacon.com/>

MooseFET

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May 5, 2007, 12:54:35 PM5/5/07

to

No, the leakage current creates a power loss in the transistors that
are needed for operation. Some of these transistors must have a
voltage drop on them or your circuit can't change any logic levels.
Any transistor with a drop on it will leak and thus generate heat.
Since your idea increases the number of transistors needed, the heat
will be a huge problem.

Radium

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May 5, 2007, 4:09:58 PM5/5/07

to

Okay. Thanks for clearing this up.

Donald

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May 5, 2007, 5:07:02 PM5/5/07

to

So I guess this means you won't patent this idea ??

Shame, with the state of the patent office, I am sure you would get it.

donald

Bob Myers

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May 6, 2007, 12:57:40 AM5/6/07

to

"Radium" <gluc...@gmail.com> wrote in message

news:1178340420....@h2g2000hsg.googlegroups.com...

> No offense but I would appreciate serious responses to my questions.
> Please leave out the dark humor.

You have yet to ask a serious question.

Bob M.

Radium

unread,

May 6, 2007, 4:08:43 AM5/6/07

to

On May 5, 9:57 pm, "Bob Myers" <nospample...@address.invalid> wrote:

> You have yet to ask a serious question.

How does SB16 ISA's FM synth freshly generate its instructions?

I want my CPU to freshly generate instructions in a similar manner
instead of playing them back from ROM.

The little lost angel

unread,

May 6, 2007, 6:37:52 AM5/6/07

to

On 4 May 2007 15:54:51 -0700, Radium <gluc...@gmail.com> wrote:

>The RAM chips store what would normally be stored in the magnetic
>platters of an HDD.

In other words, you're describing a PC without HDD, aka a PC with just
solid state storage. Which others have mentioned, already exists with
systems running off solid state storage using existing technology such
as gigabyte sizes CF storage. They even have RAID controllers that run
off such RAM.

>> Ok then what's the practical implication/advantage/whatever of what
>> you're proposing?
>
>As I said before, parallel-Hz allows massively-serial devices to
>operate at extremely high clock rates without needing any cooling
>equipment.

It doesn't. As I understand it, heat is generated by transistors
mainly during switching, i.e. when it's doing something.

Simplistically, a 4Ghz CPU generates 4 giga unit of heat when
operating at 4Ghz. A 1Hz CPU of similar output efficiency generates
1unit of heat. But you need 4 billion 1Hz CPU, that translate to a
total of 4 giga unit of heat as well. There's no heat advantage to
your system.

Furthermore, pins, packaging and wiring takes up space. Your 4 Billion
1Hz CPU will be extremely space and wiring inefficient compared to a
single 4Ghz cpu.

The latency to first instruction out is also magnitudes times faster
than your 'parallel Hz' system. A modern 4Ghz CPU can always go full
speed for 1us to produce results and shutdowns/downclock to conserve
power. But your 1Hz system cannot be faster than 1 sec. So a 4Ghz CPU
can have the same heat efficiency AND faster output. Your 4Ghz
Parallel-Hz system is not comparable.

Nick Maclaren

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May 6, 2007, 6:49:37 AM5/6/07

to

In article <463dae1b....@news.singnet.com.sg>,

a?n?g?e?l...@lovergirl.lrigrevol.moc.com (The little lost angel) writes:
|> On 4 May 2007 15:54:51 -0700, Radium <gluc...@gmail.com> wrote:
|>
|> >As I said before, parallel-Hz allows massively-serial devices to
|> >operate at extremely high clock rates without needing any cooling
|> >equipment.
|>
|> It doesn't. As I understand it, heat is generated by transistors
|> mainly during switching, i.e. when it's doing something.

That was once largely true, but isn't any longer. Look up "passive
leakage" - it is now comparable to active leakage.

Regards,
Nick Maclaren.

Don Bowey

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May 6, 2007, 9:23:24 AM5/6/07

to

On 5/6/07 1:08 AM, in article
1178438923.0...@o5g2000hsb.googlegroups.com, "Radium"
<gluc...@gmail.com> wrote:

You have yet to tell us how you plan to get your system to operate at a rate
higher than one Hz.

An idea (or daydream) is not a design. All of your questions are a waste of
time until you provide some serious answers.

So far, you continue to show yourself as a troll.

MooseFET

unread,

May 6, 2007, 9:59:08 AM5/6/07

to

On May 6, 1:08 am, Radium <gluceg...@gmail.com> wrote:
> On May 5, 9:57 pm, "Bob Myers" <nospample...@address.invalid> wrote:
>
> > You have yet to ask a serious question.
>
> How does SB16 ISA's FM synth freshly generate its instructions?

It doesn't. It does as it is told. It has built in hardware the
performs certain actions when told to. Even if it is claimed to
"generate instructions" it must be doing so based on some higher level
of instructions it is given or contains.

Consider an interpretive language such as BASIC. You can run a BASIC
program on your PC. At no time did your PC contain the instructions
for the specific program you ran and yet it did its job. The same can
be said to be true of things like sound and video cards. They are
given some collection of bits as input and make sound and light in
responce to them. The bits they are passed are not a full explanation
of the details of how to do those actions just the command that they
be done. Internal hardware inside the card fills in the details.

>
> I want my CPU to freshly generate instructions in a similar manner
> instead of playing them back from ROM.

Well I want to rich and good looking. Lets see whos wish comes true.

MooseFET

unread,

May 6, 2007, 10:11:25 AM5/6/07

to

On May 6, 3:37 am, a?n?g?...@lovergirl.lrigrevol.moc.com (The little
lost angel) wrote:
[...]

> It doesn't. As I understand it, heat is generated by transistors
> mainly during switching, i.e. when it's doing something.

This is true at 4GHz. If you run as slow as 1Hz, the "leakage" sets
the lower limit on the power.

See the bit on "power estimation" in:
http://direct.xilinx.com/bvdocs/publications/ds055.pdf

If you put zero in as the frequency, you will see some power remains.
This part has enough hardware in it to make an extremely dumb
processor.

[....]

> The latency to first instruction out is also magnitudes times faster
> than your 'parallel Hz' system. A modern 4Ghz CPU can always go full
> speed for 1us to produce results and shutdowns/downclock to conserve
> power. But your 1Hz system cannot be faster than 1 sec. So a 4Ghz CPU
> can have the same heat efficiency AND faster output. Your 4Ghz
> Parallel-Hz system is not comparable.

Actually his idea may be worse than that. If an instruction needs the
value produced by a previous one, it can't be started until the other
is done. Consider the statement:

IF (A + B) * C > D THEN E = 1

(A + B) takes a cyle
* C takes a cycle
> D takes a cycle
E = 1 takes a cycle

Thats 4 seconds to get the answer.

Quadibloc

unread,

May 6, 2007, 11:35:36 AM5/6/07

to

Radium wrote:
> Those mentifex devices are massively-parallel. As I said, my "parallel
> Hz" design is intended for applications that are serial.
.
In that case, your design won't help.

It's true that somewhere, a device starts an instruction, and then one
nanosecond later, another device can finish an instruction. But they
won't be the _same_ instruction.

So, if something depends on the answer of an instruction that finishes
at a certain time, it needs to get that answer when _that_ instruction
finishes, not another one.

Having a time offset between processors in a massively parallel system
- which is all that your system remains, despite the offset - just
means that they're not synchronized, so if you need to take the result
from one instruction finishing, and give it to _many_ of the other
processors, some time may be wasted for some of them to become
available.

John Savard

kony

unread,

May 6, 2007, 12:47:26 PM5/6/07

to

On 6 May 2007 01:08:43 -0700, Radium <gluc...@gmail.com>
wrote:

>On May 5, 9:57 pm, "Bob Myers" <nospample...@address.invalid> wrote:
>
>> You have yet to ask a serious question.
>
>How does SB16 ISA's FM synth freshly generate its instructions?
>

Because there's a CPU and code telling it what to do, which
DOESN'T freshly generate.

>I want my CPU to freshly generate instructions in a similar manner
>instead of playing them back from ROM.

OK, then stop using your present system and do that.

Mark

unread,

May 6, 2007, 1:12:41 PM5/6/07

to

Not a troll, just stupid. A troll is someone who actually knows what
they are saying is incorrect. A stupid person simply isn't smart enough
to understand that what they are saying is incorrect.

Guy Macon

unread,

May 6, 2007, 1:16:46 PM5/6/07

to

The little lost angel wrote:

>It doesn't. As I understand it, heat is generated by transistors
>mainly during switching, i.e. when it's doing something.

Your understanding is close, but not exactly correct.
Look at Figure 2 in this Chip Design Magazine article:
http://www.chipdesignmag.com/print.php?articleId=76?issueId=6

Also see:
http://www.research.ibm.com/journal/rd/504/frank.html
http://www.gabeoneda.com/node/79
http://www.eetimes.com/showArticle.jhtml?articleID=54202129
http://www.dspdesignline.com/showArticle.jhtml?printableArticle=true&articleId=21400746
http://en.wikipedia.org/wiki/Power_optimization_(EDA)

Guy Macon
<http://www.guymacon.com/>

Guy Macon

unread,

May 6, 2007, 1:24:20 PM5/6/07

to

Mark wrote:

>Not a troll, just stupid. A troll is someone who actually knows what
>they are saying is incorrect. A stupid person simply isn't smart enough
>to understand that what they are saying is incorrect.

From the Jargon file:

-----------------------------------------------------------------------

Troll

1. v.,n. [From the Usenet group alt.folklore.urban] To utter a posting
on Usenet designed to attract predictable responses or flames; or, the
post itself. Derives from the phrase "trolling for newbies" which in
turn comes from mainstream "trolling", a style of fishing in which one
trails bait through a likely spot hoping for a bite.
The well-constructed troll is a post that induces lots of newbies and
flamers to make themselves look even more clueless than they already do,
while subtly conveying to the more savvy and experienced that it is in
fact a deliberate troll. If you don't fall for the joke, you get to be
in on it. See also YHBT.

2. n. An individual who chronically trolls in sense 1; regularly posts
specious arguments, flames or personal attacks to a newsgroup,
discussion list, or in email for no other purpose than to annoy someone
or disrupt a discussion. Trolls are recognizable by the fact that they
have no real interest in learning about the topic at hand - they simply
want to utter flame bait. Like the ugly creatures they are named after,
they exhibit no redeeming characteristics, and as such, they are
recognized as a lower form of life on the net, as in, "Oh, ignore him,
he's just a troll."

Some people claim that the troll (sense 1) is properly a narrower
category than flame bait, that a troll is categorized by containing
some assertion that is wrong but not overtly controversial.

The use of `troll' in either sense is a live metaphor that readily
produces elaborations and combining forms. For example, one not
infrequently sees the warning "Do not feed the troll" as part of
a followup to troll postings.

Robert Redelmeier

unread,

May 6, 2007, 1:57:18 PM5/6/07

Multiplies usually take more than one cycle.

>> > D takes a cycle

The "THEN" (a conditional branch) also takes a cycle (unless you do
E = 1 as a conditional move).

>> E = 1 takes a cycle
>
> Not necessarily. The "E = 1" step can be done in zero cycles. It's
> just a mux of '1' and whatever was there. There are several ways of
> handling this in zero cycles. Fer instance one could do it by
> assigning one register ('1') or another (the previous 'E') during
> rename.

So E = 1; F = 2; G = 3; H = 4; I = 5; also takes zero cycles in total???

Moves don't take zero cycles. Although they are pretty simple, they
need resources such as a constant decoder and a register port to
write the result to. So moves take 1 cycle just like any other basic
ALU instructions.

>> Thats 4 seconds to get the answer.

It's 5 with the branch (1 cycle if not-taken), and if you assume all variables were
allocated to registers and a multiply take just one cycle. But remember that the
OP was proposing a simple bit-serial CPU, so if registers are 32 bits wide, and
the multiply is done bit-serially too, it would take 1152 seconds to complete!

Wilco

MooseFET

unread,

May 7, 2007, 9:43:06 AM5/7/07

to

On May 7, 3:42 am, "Wilco Dijkstra" <Wilco_dot_Dijks...@ntlworld.com>
wrote:

> "krw" <k...@att.bizzzz> wrote in message
>
> news:MPG.20a82723e...@news.individual.net...
>

> > In article <1178460685.878244.238...@e65g2000hsc.googlegroups.com>,
> > kensm...@rahul.net says...

> >> Actually his idea may be worse than that. If an instruction needs the
> >> value produced by a previous one, it can't be started until the other
> >> is done. Consider the statement:
>
> >> IF (A + B) * C > D THEN E = 1
>
> >> (A + B) takes a cyle
> >> * C takes a cycle
>
> Multiplies usually take more than one cycle.

Typically they do but no law of the universe enforces this. You can
have a fast multiplier that does the job in one cycle. This is a lot
easier to do if the word length is small. As a result we can't hold
him to it taking more cycles.

>
> >> > D takes a cycle
>
> The "THEN" (a conditional branch) also takes a cycle (unless you do
> E = 1 as a conditional move).

There are a few porcessors out there that have other conditionals. The
ATT DSP chip had several such instuctions. So we can't hold him to
that either.

Naturally, if both of these things were included in the processors he
was repeating a billion times, the power would certainly be much
higher.

[....]

> It's 5 with the branch (1 cycle if not-taken), and if you assume all variables were
> allocated to registers and a multiply take just one cycle. But remember that the
> OP was proposing a simple bit-serial CPU, so if registers are 32 bits wide, and
> the multiply is done bit-serially too, it would take 1152 seconds to complete!

Atually if it is very simple, you need 32*65 shifts. The 64 bit output
area needs to go around one full cycle to do the add and then one
extra to align for the next bit. Only if you use some extra logic do
you get it down to a lower value.

MooseFET

unread,

May 7, 2007, 9:45:35 AM5/7/07

to

On May 6, 11:25 pm, a?n?g?...@lovergirl.lrigrevol.moc.com (The little
lost angel) wrote:

> On 6 May 2007 07:11:25 -0700, MooseFET <kensm...@rahul.net> wrote:
>
> >Actually his idea may be worse than that. If an instruction needs the
> >value produced by a previous one, it can't be started until the other
> >is done. Consider the statement:
>
> > IF (A + B) * C > D THEN E = 1
>
> >(A + B) takes a cyle
> >* C takes a cycle
> >> D takes a cycle
> >E = 1 takes a cycle
>
> >Thats 4 seconds to get the answer.
>
> I mentioned this earlier to him albeit without detailed example. But
> Radium seems to conveniently overlooked it so I figured he's probably
> not going to answer even if I repeated it a second time. Or maybe he
> didn't understand the implications of my statement but let's see if he
> does with your detailed example :ppPp

I think it is likely he didn't understand your point. He appears to
be inteligent but ignorant. He didn't know where the leakage current
happened for example.

krw

unread,

May 7, 2007, 10:41:39 AM5/7/07

to

In article <BoD%h.7035$H4....@newsfe2-gui.ntli.net>,
Wilco_dot...@ntlworld.com says...

>
> "krw" <k...@att.bizzzz> wrote in message
> news:MPG.20a82723e...@news.individual.net...
> > In article <1178460685.8...@e65g2000hsc.googlegroups.com>,
> > kens...@rahul.net says...
>
> >> Actually his idea may be worse than that. If an instruction needs the
> >> value produced by a previous one, it can't be started until the other
> >> is done. Consider the statement:
> >>
> >> IF (A + B) * C > D THEN E = 1
> >>
> >> (A + B) takes a cyle
> >> * C takes a cycle
>
> Multiplies usually take more than one cycle.

Usually, but not necessarily. Some processors do an fused multiply-
add too, saving another cycle ( [(A+B)] * [C-D] > 0). That wasn't
the issue though.

>
> >> > D takes a cycle
>
> The "THEN" (a conditional branch) also takes a cycle (unless you do
> E = 1 as a conditional move).

Nope. That's in the compare.

> >> E = 1 takes a cycle
> >
> > Not necessarily. The "E = 1" step can be done in zero cycles. It's
> > just a mux of '1' and whatever was there. There are several ways of
> > handling this in zero cycles. Fer instance one could do it by
> > assigning one register ('1') or another (the previous 'E') during
> > rename.
>
> So E = 1; F = 2; G = 3; H = 4; I = 5; also takes zero cycles in total???

I don't see F, G, H, and I in the problem. Who said anything about
total cycles being zero?

> Moves don't take zero cycles.

They certainly can. A processor with register renaming can certainly
do a move in zero cycles. In this case, all the MOVE does is change
pointers in the register file. BTW, some processors even to
exchanges in zero cycles.

> Although they are pretty simple, they
> need resources such as a constant decoder

WTF do I need a "constant decoder"?

> and a register port to write the result to.

Nope. Just change the register name(s).

> So moves take 1 cycle just like any other basic
> ALU instructions.

Nope. They can be hidden since they need not use the ALU at all,
just a change to the rename file. Note that this move isn't an
independent instruction, so it's even easier to hide the move (a
rename is required at the completion of every arithmetic instruction
anyway).

> >> Thats 4 seconds to get the answer.
>
> It's 5 with the branch (1 cycle if not-taken), and if you assume all variables were
> allocated to registers and a multiply take just one cycle. But remember that the
> OP was proposing a simple bit-serial CPU, so if registers are 32 bits wide, and
> the multiply is done bit-serially too, it would take 1152 seconds to complete!

Branches can be predicted or speculatively executed with the
rename/completion contingent on the results. There are all sorts of
games that can be played to save cycles.

--
Keith

Wilco Dijkstra

unread,

May 7, 2007, 11:49:32 AM5/7/07

to

"krw" <k...@att.bizzzz> wrote in message

news:MPG.20a8fba8c...@news.individual.net...

> In article <BoD%h.7035$H4....@newsfe2-gui.ntli.net>,
> Wilco_dot...@ntlworld.com says...
>>
>> "krw" <k...@att.bizzzz> wrote in message
>> news:MPG.20a82723e...@news.individual.net...
>> > In article <1178460685.8...@e65g2000hsc.googlegroups.com>,
>> > kens...@rahul.net says...
>>
>> >> Actually his idea may be worse than that. If an instruction needs the
>> >> value produced by a previous one, it can't be started until the other
>> >> is done. Consider the statement:
>> >>
>> >> IF (A + B) * C > D THEN E = 1
>> >>
>> >> (A + B) takes a cyle
>> >> * C takes a cycle
>>
>> Multiplies usually take more than one cycle.
>
> Usually, but not necessarily. Some processors do an fused multiply-
> add too, saving another cycle ( [(A+B)] * [C-D] > 0). That wasn't
> the issue though.

Sure. I was just pointing out that the example will take a lot longer than you
might think. There are a lot of unstated assumptions here (register based
architecture etc)...

>> >> > D takes a cycle
>>
>> The "THEN" (a conditional branch) also takes a cycle (unless you do
>> E = 1 as a conditional move).
>
> Nope. That's in the compare.

Few architectures combine a compare and branch, MIPS is one of the few
that can do that, but even MIPS cannot do the above comparison and branch
in one instruction.

>> >> E = 1 takes a cycle
>> >
>> > Not necessarily. The "E = 1" step can be done in zero cycles. It's
>> > just a mux of '1' and whatever was there. There are several ways of
>> > handling this in zero cycles. Fer instance one could do it by
>> > assigning one register ('1') or another (the previous 'E') during
>> > rename.
>>
>> So E = 1; F = 2; G = 3; H = 4; I = 5; also takes zero cycles in total???
>
> I don't see F, G, H, and I in the problem. Who said anything about
> total cycles being zero?

If you claim that E = 1 takes zero cycles then it follows that any similar
assignment takes zero cycles and thus my example would take zero
cycles. Instructions do not take zero cycles.

>> Moves don't take zero cycles.
>
> They certainly can. A processor with register renaming can certainly
> do a move in zero cycles. In this case, all the MOVE does is change
> pointers in the register file. BTW, some processors even to
> exchanges in zero cycles.

Yes it is possible for a move to be implemented using register renaming
in an advanced CPU rather than using the ALU. However this only applies
to register-register moves, not constant moves. And it still doesn't mean
the move takes zero cycles. An advanced implementation could make
moves have zero cycle *latency*, but no CPU I know of does that.

>> Although they are pretty simple, they
>> need resources such as a constant decoder
>
> WTF do I need a "constant decoder"?

Constants need to be extracted from the instructions, the bits grouped
together if not adjacent already and zero or signextended to the register
width. On some architectures constants can include a shift or expand into
a pattern like AB00AB00. So you always need to decode the constant
before it can be used.

>> and a register port to write the result to.
>
> Nope. Just change the register name(s).

Change the name to what exactly? Register renaming can only rename
registers to other registers, not constants to registers...

>> So moves take 1 cycle just like any other basic
>> ALU instructions.
>
> Nope. They can be hidden since they need not use the ALU at all,
> just a change to the rename file. Note that this move isn't an
> independent instruction, so it's even easier to hide the move (a
> rename is required at the completion of every arithmetic instruction
> anyway).

Which particular CPU are you talking about? An advanced CPU would
have executed E = 1 long before it had done any of the other instructions,
without using any register renaming tricks.

>> >> Thats 4 seconds to get the answer.
>>
>> It's 5 with the branch (1 cycle if not-taken), and if you assume all variables were
>> allocated to registers and a multiply take just one cycle. But remember that the
>> OP was proposing a simple bit-serial CPU, so if registers are 32 bits wide, and
>> the multiply is done bit-serially too, it would take 1152 seconds to complete!
>
> Branches can be predicted or speculatively executed with the
> rename/completion contingent on the results. There are all sorts of
> games that can be played to save cycles.

Sure. But the issue was how long a simple CPU like the OP proposed would take.
You're thinking of Pentium-class CPUs, but we're talking about far far simpler CPUs
executing at best 1 instruction per cycle (or 1 every N cycles for N-bit serial).

Wilco

Rich Grise

unread,

May 7, 2007, 2:27:16 PM5/7/07

to

On Sun, 06 May 2007 01:08:43 -0700, Radium wrote:

> On May 5, 9:57 pm, "Bob Myers" <nospample...@address.invalid> wrote:
>
>> You have yet to ask a serious question.
>
> How does SB16 ISA's FM synth freshly generate its instructions?
>

SB16 ISA's FM synth doesn't freshly generate its instructions.

It freshly synthesizes (electrical representations of) sounds based on
instructions it receives from the device that owns, and is controlling,
the ISA bus.

> I want my CPU to freshly generate instructions in a similar manner
> instead of playing them back from ROM.

Go ahead! Build one and show us how it's done! If you're just trying
to convince somebody to do the work for you, then offer money. ;-)

If you're looking for someone to show you how to implement your
ideas, then please learn how to visit the astral plane.

Good Luck!
Rich

Radium

unread,

May 7, 2007, 2:35:43 PM5/7/07

to

On May 7, 11:27 am, Rich Grise <r...@example.net> wrote:

> On Sun, 06 May 2007 01:08:43 -0700, Radium wrote:

> > On May 5, 9:57 pm, "Bob Myers" <nospample...@address.invalid> wrote:

> >> You have yet to ask a serious question.

> > How does SB16 ISA's FM synth freshly generate its instructions?

> SB16 ISA's FM synth doesn't freshly generate its instructions.

> It freshly synthesizes (electrical representations of) sounds based on
> instructions it receives from the device that owns, and is controlling,
> the ISA bus.

Okay. That is what I meant. Sorry for the misunderstanding.

I want my CPU to freshly generate electronic signals [instead of
playing them back from ROM] "based on instructions it receives from
the device that owns, and is controlling" it.

Thanks for clearing this up.

Sometimes, I need to be told what I want.

Wilco Dijkstra

unread,

May 7, 2007, 3:12:49 PM5/7/07

to

"Radium" <gluc...@gmail.com> wrote in message

news:1178562943.5...@l77g2000hsb.googlegroups.com...

So you want micro code :-) But where do you get the instructions that
control the micro code from? Or are you generating those instructions
too? If so, where do those instructions come from? And so on...

You always need to store and play back instructions one way or another,
they can't generate themselves automatically you know. Lots of people
would be out of a job if computers could write their own software...

> Thanks for clearing this up.
>
> Sometimes, I need to be told what I want.

Thanks for making my day!

Wilco

kony

unread,

May 7, 2007, 3:54:56 PM5/7/07

to

On 7 May 2007 11:35:43 -0700, Radium <gluc...@gmail.com>
wrote:

>I want my CPU to freshly generate electronic signals [instead of
>playing them back from ROM] "based on instructions it receives from
>the device that owns, and is controlling" it.

So you want to pervert the CPU into a device that doesn't
process. Once you have that new non-CPU device, all you'd
have to do is then add a CPU to the system in addition to
this new device so you can regain the functions you stripped
away.

Del Cecchi

unread,

May 7, 2007, 3:56:42 PM5/7/07

to

Of course one can generate the instructions to the sound card
algorithmically rather that using stored sequences. Likewise with Just
in Time compilation or interpretation, one can generate sequences of
instructions algorithmically rather than use a classic stored object
program. Just think, a digital theramin.

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”

Rich Grise

unread,

May 7, 2007, 4:50:12 PM5/7/07

to

On Fri, 04 May 2007 17:45:56 -0700, Radium wrote:

> On May 4, 5:32 pm, "Bob Myers" <nospample...@address.invalid> wrote:
>
>> Yes, you've SAID that before, but you have yet to give
>> any indication at all that it means anything.
>
> How does it not mean anything?

By not meaning anything.

Here's how to find out:

Get a piece of paper and a pencil or pen, and write down exactly what
it _does_ mean, in plain English. That should help to understand the
phrase "doesn't mean anything."

Good Luck!
Rich

Rich Grise

unread,

May 7, 2007, 4:54:56 PM5/7/07

to

On Mon, 07 May 2007 14:56:42 -0500, Del Cecchi wrote:
...

Just think, a digital theramin.

OK:
http://www.physics.gla.ac.uk/~kskeldon/PubSci/exhibits/E9/cir2.gif

;-)
Rich

Wilco Dijkstra

unread,

May 7, 2007, 4:58:00 PM5/7/07

to

"Del Cecchi" <cecchi...@us.ibm.com> wrote in message
news:5a9ejsF...@mid.individual.net...

But in these cases there is another program that does the generation/translation/
interpretation/decompression. That program itself must be stored and played back
from memory somehow.

In any case the data used to generate the instructions from is a stored program
as well that is simply played back from memory. Does it matter whether the same
binary can be intepreted, JIT'd, executed as micro code sequences or directly
executed by different implementations? In many cases you can't tell, eg. Transmeta.
I call that binary a stored program played back from memory irrespectively of how
it is executed.

Wilco

Bob Myers

unread,

May 7, 2007, 5:11:52 PM5/7/07

to

"Rich Grise" <ri...@example.net> wrote in message
news:pan.2007.05.07....@example.net...

> On Fri, 04 May 2007 17:45:56 -0700, Radium wrote:
>
>> On May 4, 5:32 pm, "Bob Myers" <nospample...@address.invalid> wrote:
>>
>>> Yes, you've SAID that before, but you have yet to give
>>> any indication at all that it means anything.
>>
>> How does it not mean anything?
>
> By not meaning anything.

Exactly....welcome to Radium's Department
of Redundancy Department.

"When I use a word, it means just what I choose it
to mean - neither more nor less."

- Humpty Dumpty, to Alice,
"Alice's Adventures in Wonderland"

Bob M.

Radium

unread,

May 7, 2007, 5:29:29 PM5/7/07

to

On May 7, 12:12 pm, "Wilco Dijkstra" <Wilco_dot_Dijks...@ntlworld.com>
wrote:

> "Radium" <gluceg...@gmail.com> wrote in message
>
> news:1178562943.5...@l77g2000hsb.googlegroups.com...

> > On May 7, 11:27 am, Rich Grise <r...@example.net> wrote:

> >> On Sun, 06 May 2007 01:08:43 -0700, Radium wrote:

> >> > On May 5, 9:57 pm, "Bob Myers" <nospample...@address.invalid> wrote:

> >> >> You have yet to ask a serious question.

> >> > How does SB16 ISA's FM synth freshly generate its instructions?

> >> SB16 ISA's FM synth doesn't freshly generate its instructions.

> >> It freshly synthesizes (electrical representations of) sounds based on
> >> instructions it receives from the device that owns, and is controlling,
> >> the ISA bus.
>
> > Okay. That is what I meant. Sorry for the misunderstanding.
>
> > I want my CPU to freshly generate electronic signals [instead of
> > playing them back from ROM] "based on instructions it receives from
> > the device that owns, and is controlling" it.

> So you want micro code :-) But where do you get the instructions that
> control the micro code from?

No microcode.

> Or are you generating those instructions
> too?

Yes.

> If so, where do those instructions come from?

Hardware logic.

If you read the wikipedia links I posted and quoted, you'll find that
there is a real-time, hardware-based alternative to ROM and microcode.

Radium

unread,

May 7, 2007, 5:35:51 PM5/7/07

to

On May 7, 12:56 pm, Del Cecchi <cecchinos...@us.ibm.com> wrote:

> one can generate sequences of
> instructions algorithmically rather than use a classic stored object
> program.

Obviously, I prefer the former over the latter. I like real-time
hardware. I dislike latency and buffering and want the least of them
as possible. In order to have the least amount of latency and
buffering, all parts of the PC must be fully-hardware with as little
software as necessary.

Rich Grise

unread,

May 7, 2007, 5:56:01 PM5/7/07

to

OK, then just go ahead and design the hardware algorithms that generate
the programs that do what you want them to do, and show us.

Even a block diagram would be fine. :-)

BTW, Radium, are you, by any chance, autistic?

Thanks!
Rich

Radium

unread,

May 7, 2007, 6:57:58 PM5/7/07

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On May 7, 2:56 pm, Rich Grise <r...@example.net> wrote:

> On Mon, 07 May 2007 14:35:51 -0700, Radium wrote:

> > On May 7, 12:56 pm, Del Cecchi <cecchinos...@us.ibm.com> wrote:

> >> one can generate sequences of
> >> instructions algorithmically rather than use a classic stored object
> >> program.

> > Obviously, I prefer the former over the latter. I like real-time
> > hardware. I dislike latency and buffering and want the least of them
> > as possible. In order to have the least amount of latency and
> > buffering, all parts of the PC must be fully-hardware with as little
> > software as necessary.

> OK, then just go ahead and design the hardware algorithms that generate
> the programs that do what you want them to do, and show us.

I wish commercial PCs were made that way. Sadly, my wish is way too
good to ever be true.

> Even a block diagram would be fine. :-)

LOL.

> BTW, Radium, are you, by any chance, autistic?

I am Aspergered.

joseph2k

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May 7, 2007, 8:47:58 PM5/7/07

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Robert Redelmeier wrote:

Add an HDMI output to that for all the large wide-screen types. The added
resolution is quite worth it.
--
JosephKK
Gegen dummheit kampfen die Gotter Selbst, vergebens.
--Schiller

Rich Grise

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May 7, 2007, 9:07:57 PM5/7/07

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On Mon, 07 May 2007 15:57:58 -0700, Radium wrote:
> On May 7, 2:56 pm, Rich Grise <r...@example.net> wrote:

...

>> BTW, Radium, are you, by any chance, autistic?
>
> I am Aspergered.

Thanks for this.

Would you like special kid-glove treatment, or is your condition under
control enough that our feedback is bearable?

Thanks,
Rich