ZPU and endians revisited

[Hieronymus vanWontz]

Hi all,

seems there's not much activity on this list, but I'll give it a try..

There's obviously been some discussion about endians in a Parallax developer group, but not sure if it has been resolved.
I gave the -mno-bytesbig gcc switch a go, but found out it's not effective on the zpu_small due to the emulation microcode still doing the big endian thing.

Has anyone dived into this any deeper and has gotten a multilib setup up that he could/would want to share?

The reason why I'd go for 'ugly' little endian (well, I'm an 68k child) is that there's quite some SoC addressing logic around the Zealot zpu_small implementation that operates on another little endian processor as well. For the larger FPGAs, I'd want to be able to swap out processors. On the small FPGAs I wanted to avoid to re-generating the I/O decoding logic in little endian, but I'm bound to the ZPU due to its little logic hunger.

So what I am doing right now on the I/O address space: All accesses are 32 bit wide, even if the registers use less bits. This also cooks down on the cycles, when no emulated instructions (loadh/loadb etc.) are used. On the other hand, it requires some switching (or CPP fun) in the processor architecture agnostic I/O access routines that is ugly. And when a direct 16 bit access is used on the I/O space accidentally, it will obviously fail on big endian. This introduces some "fun" on the gdb scripting side and makes some debugging prone to errors. So the little endian architecture would be a little more tolerant to access widths on the I/O space.

Any thoughts?

Cheers,

- Martin