Pipelined ZPU (again..)

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Hieronymus vanWontz

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Sep 2, 2015, 1:57:42 PM9/2/15
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Hi all,

not sure if this mailing list is being much watched anymore, but I thought I'd share this with you ZPU folks: It's about another ZPU variant (some might say: Oh, not again), pipelined (3 stage), written/verified in MyHDL, and the full debug dance of course. I'm not yet done with the full regression testing, it's kinda in a state "works for me" (swaps against Zealot). Logic usage is about factor 1.5 compared to the Zealot with the ICE patch, but that depends a bit on the FPGA architecture and tools. It's not really fast in terms of max clk, but will typically do things in one cycle (except ALU and I/O which go up to 3 cycles).
Some sneak peek (virtualized, sorry for the evil flash): http://section5.ch/files/masocist-opensource-v0.1alpha_eval/doc/movies/02_debug.html
I'm not yet there to go full opensource with the whole package, but if someone wants to play, I'm happy to send working VHDL. Verilog output hasn't been tested.

Cheers,
- Da Wonz

Edward Brekelbaum

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Sep 4, 2015, 9:04:31 AM9/4/15
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Nice!

Michael Schnell

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Sep 7, 2015, 7:25:15 AM9/7/15
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Great !

-Michael
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