Xilinx License Solution Center

[Elia Khensamphanh]

Diveinto the data compiled from a survey of over 400 financial services professionals from around the world. The results reveal the trends, challenges, and opportunities that define the state of AI in financial services.

AI is powering change in every industry. From generative AI and speech recognition to medical imaging and improved supply chain management, AI is providing enterprises the compute power, tools, and algorithms their teams need to do their life's work.

High-performance computing (HPC) is the ability to process data and perform complex calculations at high speeds. HPC is one of the most essential tools fueling the advancement of computational science.

From developing autonomous vehicles on NVIDIA DRIVE to creating factory digital twins and retail experiences with NVIDIA Omniverse, our automotive solutions offer the performance and scalability to design, visualize, simulate, and create all types of future transportation.

From the cloud to the office to the data center to the edge, NVIDIA provides solutions that deliver breakthrough performance on enterprise AI and HPC workloads at any scale, driving business decisions in real time and resulting in faster time to value.

SMS was acquired by NVIDIA Corporation of Santa Clara, CA in May 2022 and was dissolved as a separate corporate entity. NVIDIA is incorporating SMS technology into its Omniverse platform and OpenUSD. For legacy support content please refer to the following: SMLib and NLib.

Deci was acquired by NVIDIA Corporation of Santa Clara, CA in May 2024 and was dissolved as a separate corporate entity. For legacy support content please refer to the following: Deci AI Documentation

N2 - Physical limitations found in industrial environments often restrain imaging for process tomography. When information is collected from sparse sensors, the acquired data is limited in terms of radial and angular sampling of the imaged slice. To overcome this problem, we demonstrate an efficient solution based on the parallel implementation of the sinogram recovery algorithm (SRA) for limited views in its variant based on the calculation of the coordinates of the center of mass (CoMs) of the subject under test, rather than performing the complete sinogram restoration. By introducing a modification in the existing SRA, we achieve high parallelization of each stage, making it ideal for implementation in hardware accelerated systems, such as field programmable gate arrays. The potential to parallelize the SRA is first studied in MATLAB, by processing all data projections concurrently and verifying performance by matching the results from the parallel and sequential implementations. Furthermore, the algorithm is coded in very high speed integrated circuits hardware description language, which is implemented and tested on a Xilinx Virtex 6 board. We report speedups of between three and four orders of magnitude, whereas the errors in CoMs' coordinates are reduced. 2001-2012 IEEE.

AB - Physical limitations found in industrial environments often restrain imaging for process tomography. When information is collected from sparse sensors, the acquired data is limited in terms of radial and angular sampling of the imaged slice. To overcome this problem, we demonstrate an efficient solution based on the parallel implementation of the sinogram recovery algorithm (SRA) for limited views in its variant based on the calculation of the coordinates of the center of mass (CoMs) of the subject under test, rather than performing the complete sinogram restoration. By introducing a modification in the existing SRA, we achieve high parallelization of each stage, making it ideal for implementation in hardware accelerated systems, such as field programmable gate arrays. The potential to parallelize the SRA is first studied in MATLAB, by processing all data projections concurrently and verifying performance by matching the results from the parallel and sequential implementations. Furthermore, the algorithm is coded in very high speed integrated circuits hardware description language, which is implemented and tested on a Xilinx Virtex 6 board. We report speedups of between three and four orders of magnitude, whereas the errors in CoMs' coordinates are reduced. 2001-2012 IEEE.

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