Hi your projects is awesome. I am working on my own student project for driving small lcd 320x240 directly by controlling source/gate drivers with fpga.Currently I am gathering information on existing drivers and how control an data signals are formed.
Display that I have can do 60 hz but I wan't to also try some faster modes to get some measurements of pixels response to higher clocks and also investigate overdriving, etc.
I have read your description of how you reached such a high refresh rate. But still one thing is not clear to me. You have written that in high hz modes you are controlling gate driver in a way that it is enabling two or more lines at once. As I understood you are pushing 2'b11 into STV or even 4b'1111 to activate multiple lines at once?
But the clock CPV is still limited by some value, 276 000 hz in your case. So even when activating 4 lines at once you have to do 4 clk edges to move to next 4 lines. So you are still limited by gate driver max clk and total vertical frame time is the same.
I don't understand how do you do it. Can you please explain? Or are you using some other driving method. Thanks.