Vivado Design Suite 7-series Fpga Libraries Guide
Giorgina Makara
The Arty S7 board features the new Xilinx Spartan-7 FPGA and is the latest member of the Arty FPGA development board family from Digilent. The Spartan-7 FPGA offers the most size, performance, and cost-conscious design engineered with the latest technologies from Xilinx and is fully compatible with Vivado Design Suite versions 2017.3 and newer. Putting this FPGA in the Arty form factor provides users with a wide variety of I/O and expansion options. Use the dual row Arduino connectors to mount one of the hundreds of hardware compatible shields available, or use the Pmod ports with Digilent's pre-made Pmod IP blocks for a more streamlined design experience. Arty S7 was designed to be MicroBlaze ready and comes out of the box ready to use with the free Xilinx WebPack licensing with the Vivado Design Suite.
The only difference between the Arty S7-50 and Arty S7-25 is the size of the Spartan-7 part. The Spartan-7 FPGAs both have the same capabilities, but the -50 has about a 2 times larger internal FPGA than the -25. The differences between the two variants are summarized below:
The board is sold standalone, but requires either a micro USB cable or 7-15V external power supply to be powered. The external power supply must have a coaxial, center-positive connector with 2.1 mm or 2.5 mm internal diameter. When purchased from Digilent, a micro USB cable or suitable 12V, 3A power supply can added at the time of purchase.
Since the release of the Arty S7-50, several changes have been made to its design to ease the manufacturing of Arty S7-25 and S7-50 variants. At the time of writing, a purchased Arty S7-50 may arrive in the form of either a Revision C or a Revision E of the board. These revisions have no difference in capabilities, however there several design differences that are described in this manual. The revision of each board is printed on the underside of the board, near the white bar-code sticker, as seen in the figure below.
The Arty S7's Soft SoC configurations are powered by MicroBlaze processor cores. MicroBlaze is a 32-bit RISC soft processor core, designed specifically to be used in Xilinx FPGAs. The MicroBlaze processor in an Arty S7 SoC configuration is typically run at 100 MHz, though it is possible to design your SoC so that it can operate at over 200MHz. The Arty S7 supports large MicroBlaze programs with demanding memory requirements by providing 16MB of non-volatile program memory and 256MB of DDR3L RAM.
After you design your soft SoC configuration for the Arty S7 you can start writing programs for it. This is done by exporting your SoC design out of Vivado IPI and into the Xilinx Software Development Kit (XSDK), an Integrated Development Environment (IDE) for designing/debugging MicroBlaze programs in C and C++. After the IPI to XSDK handoff, XSDK is automatically configured to include libraries and examples for the peripheral blocks you've included in your SoC. At this point, programming the Arty S7 is very similar to programming other SoC or microcontroller platforms: Programs are written in C, programmed into board over USB, and then optionally debugged in hardware. Soft SoC configurations and MicroBlaze programs can also be loaded into the 16MB non-volatile program memory so that they execute immediately after Arty S7 is powered on.
Although the Arty S7 is particularly well suited for Microblaze Soft SoC designs, it can also be programmed with a Register-Transfer Level (RTL) circuit description like any other FPGA development platform. This design flow requires that you describe your RTL circuit using an HDL within Vivado, and it does not use the Vivado IPI or XSDK tools. Designing this way has many advantages, but is very unlike programming a single board computer, and instead is used by those familiar with FPGA design or interested in designing and implementing a digital circuit that doesn't contain a processor.
The Arty S7 board requires a 5 volt power source to operate. This power source can come from the Digilent USB-JTAG port (J10) or it can be derived from a 7 to 15 Volt DC power supply connected to the Power Jack (J13) or Pin 8 of Header J8.
A power-good LED (LD9), driven by the 3.3 output (VCC3V3) output of the DA9062 regulator, indicates that the board is receiving power and that the onboard supplies are functioning as expected. If this LED does not illuminate when an acceptable power supply is connected, please contact your distributor or Digilent Support for further help.
An external power supply can be used by plugging into Power Jack J13. The supply must use a coaxial, center-positive 2.1mm (or 2.5mm) internal-diameter plug, and provide a voltage of 7 to 15 Volts DC. The supply should provide a minimum current of 1 amp. Ideally, the supply should be capable of providing 36 Watts of power (12 Volts DC, 3 amps).
An external battery pack can be used by connecting the battery's positive terminal to pin 8 of J8 (labeled VIN) and the negative terminal to pin 7 of J8 (labeled GND), as shown in Figure 1.2. The battery must provide a voltage between 7 and 15 volts DC, and should NOT be installed while there is a supply connected to Power Jack J13.
The Arty S7 uses a combination of a USB load switch (IC13), a MOSFET, (Q6), and some additional control ci4cuitry to automatically determine the 5V power source based on the supplies that are plugged into the board. If an external supply is connected to Power Jack J13, it will be used as the input source regardless of whether or not anything is plugged into the USB port (J10). If the Arty S7 is initially powered via USB and an external supply is plugged into J13, then the the 5V power source will automatically switch over to the regulated external supply rail and no brown-out will occur. If the external supply is later disconnected from J13 while USB power is still present, then the 5V power source will switch over to USB power, and a brown-out - which can be seen as the power-good LED toggles - will occur.
Voltage regulator circuits from Dialog Semiconductor and Texas Instruments create the required 3.3V, 1.8V, 1.35V, 1.25V, 1.00V, 0.675V supplies from the 5V power source. In the event that an external supply or battery pack is used, the on-board Monolithic Power Systems 5V regulator (IC12) provides the 5V source. Table 1.1 provides additional information (typical currents depend strongly on FPGA configuration and the values provided are typical of medium size/speed designs).
The VCCINT (1.0V) and VCC1V8 (1.8V) rails each have a 0.010 Ohm current sense resistor for monitoring the amount of current being consumed by them. You can access them via JP3 for the VCCINT rail and JP4 for the VCC1V8 rail. To calculate the current on each power rail, use Ohm's law with R=0.010 and V equal to the measured voltage across the jumper. To measure the voltage you can use an external digital multimeter or oscilloscope.
A Spartan-7 50T bitstream is typically 17,536,096 bits. The time it takes to program the Arty S7 can be decreased by compressing the bitstream before programming, and then allowing the FPGA to decompress the bitstream itself during configuration. Depending on design complexity, compression ratios of 10x can be achieved. Bitstream compression can be enabled within the Xilinx tools to occur during generation. For instructions on how to do this, consult the Xilinx documentation for the toolset being used.
The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J10) or an external JTAG programmer, such as the Digilent JTAG-HS2, attached to port J9. You can perform JTAG programming any time after the Arty S7 has been powered on, regardless of whether the mode jumper (JP1) is set. If the FPGA is already configured, then the existing configuration is overwritten with the bitstream being transmitted over JTAG. Not setting the mode jumper (seen in Figure 2.1) is useful to prevent the FPGA from being configured from Quad-SPI Flash until a JTAG programming occurs.
Since the FPGA's memory on the Arty S7 is volatile, it relies on the Quad-SPI flash memory to store the configuration between power cycles. This configuration mode is called Master SPI. The blank FPGA takes the role of master and reads the configuration file out of the flash device upon power-up. To that effect, a configuration file needs to be downloaded first to the flash. When programming a non-volatile flash device, a bitstream file is transferred to the flash in a two-step process. First, the FPGA is programmed with a circuit that can program flash devices, and then data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx tools). This is called indirect programming. After the flash device has been programmed, it can automatically configure the FPGA at a subsequent power-on or reset event as determined by the mode jumper setting (see Figure 2.1). Programming files stored in the flash device will remain until they are overwritten, regardless of power-cycle events.
The Arty S7 includes one MT41K128M16JT-125 memory component, creating a single rank, 16-bit wide interface. It is routed to a 1.35V-powered HR (High Range) FPGA bank with 50 ohm controlled single-ended trace impedance. 50 ohm internal terminations in the FPGA are used to match the trace characteristics. Similarly, on the memory side, on-die terminations (ODT) are used for impedance matching.
For proper operation of the memory, a memory controller and physical layer (PHY) interface needs to be included in the FPGA design. The easiest way to accomplish this on the Arty S7 is to use the Xilinx 7-series memory interface solutions core generated by the MIG (Memory Interface Generator) Wizard. The MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect to user logic. This workflow allows the customization of several DDR parameters optimized for the particular application. Table 3.1 below lists the MIG Wizard settings optimized for the Arty S7 (any settings not mentioned can be left in default state).
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