[yalo commit] r128 - wiki
codesite...@google.com
Date: Tue Feb 24 07:02:46 2009
New Revision: 128
Modified:
wiki/AssemblyX64C.wiki
wiki/AssemblyX64Overview.wiki
Log:
wiki: correct cmov to cmovcc, format bullets in a single line (seems
wiki syntax does not support multi-line lists?).
Modified: wiki/AssemblyX64C.wiki
==============================================================================
--- wiki/AssemblyX64C.wiki (original)
+++ wiki/AssemblyX64C.wiki Tue Feb 24 07:02:46 2009
@@ -27,12 +27,12 @@
--------
-= cmov: Conditional Move =
+= cmovcc: Conditional Move =
-|| Instruction || Opcode || 64-Bit Mode || 16/32-Bit Mode
|| Description ||
-|| cmov r16 r/m16 || o16 0F (+ 40 cc) /r || Valid || Valid
|| ||
-|| cmov r32 r/m32 || o32 0F (+ 40 cc) /r || Valid || Valid
|| ||
-|| cmov r64 r/m64 || 0F (+ 40 cc) /r || Valid || ~~N.E.~~
|| ||
+|| Instruction || Opcode || 64-Bit Mode || 16/32-Bit
Mode || Description ||
+|| cmovcc r16 r/m16 || o16 0F (+ 40 cc) /r || Valid ||
Valid || ||
+|| cmovcc r32 r/m32 || o32 0F (+ 40 cc) /r || Valid ||
Valid || ||
+|| cmovcc r64 r/m64 || 0F (+ 40 cc) /r || Valid ||
~~N.E.~~ || ||
Please refer [AssemblyX64Overview#Conditional_Codes conditional codes] for
details.
Modified: wiki/AssemblyX64Overview.wiki
==============================================================================
--- wiki/AssemblyX64Overview.wiki (original)
+++ wiki/AssemblyX64Overview.wiki Tue Feb 24 07:02:46 2009
@@ -25,8 +25,7 @@
For columns *64-bit Mode* and *16/32-bit Mode*, following notations are
used:
* *Valid*: supported.
* *Invalid*: not supported.
- * *N.E.*: not encodable. The opcode may be part of a sequence of other
- valid instructions.
+ * *N.E.*: not encodable. The opcode may be part of a sequence of other
valid instructions.
* *N.S.*: not supported. The instruction requires an address override
prefix.
= Notations for Instructions =
@@ -34,24 +33,15 @@
Following notations are used:
* *imm8*: immediate byte value in the range of -128..+255.
* *imm16*: immediate word value in the range of -32,768..+65,535.
- * *imm32*: immediate doubleword value in the range of
- -2,147,483,648..+4,294,967,295.
- * *imm64*: immediate quadword value in the range of
- -9,223,372,036,854,775,808..+18,446,744,073,709,551,615..
- * *!r8*: one of the byte general-purpose registers: al, cl, dl, bl, ah,
ch,
- dh, bh, bpl, spl, dil, and sil.
- * *!r16*: one of the word general-purpose registers: ax, cx, dx, bx, sp,
bp,
- si, di.
- * *!r32*: one of the doubleword general-purpose registers: eax, ecx, edx,
ebx,
- esp, ebp, esi, edi.
- * *!r64*: one of the quadword general-purpose registers: rax, rcx, rdx,
rbx,
- rsp, rbp, rsi, rdi, !r8-!r15.
- * *m8, m16, m32, m64*: memory references. Specifier (`byte`, `word`,
`dword`, `qword`)
- is needed for ambiguous cases. For example in `(mov word [12345] 16).
- * *m16&32*, *m16&16*, *m32&32*, *m16&64*, a memory operand containing one
pair whose sizes
- are indicated on the left and right size of the ampersand.
- * *r/m8, r/m16, r/m32, r/m64*: register or memeory choices. For example,
r/m8
- means that either r8 or m8 can be used as operand.
+ * *imm32*: immediate doubleword value in the range of
-2,147,483,648..+4,294,967,295.
+ * *imm64*: immediate quadword value in the range of
-9,223,372,036,854,775,808..+18,446,744,073,709,551,615..
+ * *!r8*: one of the byte general-purpose registers: al, cl, dl, bl, ah,
ch, dh, bh, bpl, spl, dil, and sil.
+ * *!r16*: one of the word general-purpose registers: ax, cx, dx, bx, sp,
bp, si, di.
+ * *!r32*: one of the doubleword general-purpose registers: eax, ecx, edx,
ebx, esp, ebp, esi, edi.
+ * *!r64*: one of the quadword general-purpose registers: rax, rcx, rdx,
rbx, rsp, rbp, rsi, rdi, !r8-!r15.
+ * *m8, m16, m32, m64*: memory references. Specifier (`byte`, `word`,
`dword`, `qword`) is needed for ambiguous cases. For example in `(mov word
[12345] 16).
+ * *m16&32*, *m16&16*, *m32&32*, *m16&64*, a memory operand containing one
pair whose sizes are indicated on the left and right size of the ampersand.
+ * *r/m8, r/m16, r/m32, r/m64*: register or memeory choices. For example,
r/m8 means that either r8 or m8 can be used as operand.
* *sreg*: segment register.
== Range of Immediate Values ==
@@ -74,25 +64,13 @@
Following notations are used:
* A hex number, such as CC, indicates a fixed byte containing that number.
- * A hex number followed by *+r*, like *B0+r*, indicates that one of the
operands
- is a register, and correspondign register value should be added to the
opcode.
- * */n* (where n is 0 to 7): indictes that one of the operand is r/m, and
the field
- Reg/Opcode should be encoded with n.
- * */r*: ModR/M byte of the instruction contains a register operand
(encoded in
- field Reg/Opcode) and an r/m operand (encoded in field R/M).
- * *rb, rw, rd, ro*: one of the operands is an immediate value, and the
- _difference_ between this value and the end address of the instruction
is
- to be encoded as byte (rb), little-endian word (rw), little-endian
-doubleword (rd), and little-endian quadword (ro) respectively.
- * *ib, iw, id, io*: one of the operands is an immediate value, and it is
to be
- encoded as byte (rb), little-endian word (rw), little-endian doubleword
(rd),
- and little-endian quadword (ro) respectively.
- * *o16, o32*: operand-size override prefix. o16 generates no code in
- 16-bit mode, but indicates a 66h prefix in 32/64-bit mode; similarly,
o32 generates
- no code in 32/64-bit mode, but indicates a 66h prefix in 16-bit mode.
- * *a16, a32*: address-size override prefix. a16 generates no code in
- 16-bit mode, but indicates a 67h prefix in 32/64-bit mode; similarly,
a32 generates
- no code in 32/64-bit mode, but indicates a 67h prefix in 16-bit mode.
+ * A hex number followed by *+r*, like *B0+r*, indicates that one of the
operands is a register, and correspondign register value should be added to
the opcode.
+ * */n* (where n is 0 to 7): indictes that one of the operand is r/m, and
the field Reg/Opcode should be encoded with n.
+ * */r*: ModR/M byte of the instruction contains a register operand
(encoded in field Reg/Opcode) and an r/m operand (encoded in field R/M).
+ * *rb, rw, rd, ro*: one of the operands is an immediate value, and the
_difference_ between this value and the end address of the instruction is
to be encoded as byte (rb), little-endian word (rw), little-endian
doubleword (rd), and little-endian quadword (ro) respectively.
+ * *ib, iw, id, io*: one of the operands is an immediate value, and it is
to be encoded as byte (rb), little-endian word (rw), little-endian
doubleword (rd), and little-endian quadword (ro) respectively.
+ * *o16, o32*: operand-size override prefix. o16 generates no code in
16-bit mode, but indicates a 66h prefix in 32/64-bit mode; similarly, o32
generates no code in 32/64-bit mode, but indicates a 66h prefix in 16-bit
mode.
+ * *a16, a32*: address-size override prefix. a16 generates no code in
16-bit mode, but indicates a 67h prefix in 32/64-bit mode; similarly, a32
generates no code in 32/64-bit mode, but indicates a 67h prefix in 16-bit
mode.
Note that REX prefix are not used in opcode notations. The prefix is
automatically generated by analyzing the operands.