The PSP 103 NQS model makes use of the "idt" function (time integration), which Xyce/ADMS does not support.
The primary reason for this is that Xyce itself doesn't have a one-size-fits-all time integration feature that could be leveraged easily to work with Verilog-A.
There is no reason that Xyce *couldn't* have such a feature, but it didn't exist at the time that Xyce/ADMS was under development and as far as I know doesn't exist yet. Every hand-coded model in Xyce that does some sort of time integration did so via some one-off code that doesn't map easily onto a generic feature.
This is the main reason that none of the Verilog-A derived models in Xyce have NQS enabled.
There is no quick and dirty workaround. If, however, Xyce were to have an easily accessible means of coding time integration so that Verilog-A's "idt" function could readily be mapped onto it, it wouldn't be hard to add to Xyce/ADMS or whatever replacement gets implemented.