I have a vendor-supplied model for an IC (under NDA, so I can't share it). It uses some behavioral sections as well as some detailed device sections.
In implementing behavioral sections of a schematic for simulation, one of the idioms or cliche's that people use is illustrated by this short netlist:
V1 1 0 sin(5 5 100k)
V2 2 0 1
Etest 3 0 value={IF(V(1)>2.5,1,0)}
R1 3 0 1k
*
.tran 10n 100u
.print tran FORMAT=RAW V(*)
.end
Xyce does not like the IF statement in the controlled voltage source line - it runs up to the point where the condition changes, and then changes the time step until it reaches the minimum, and gives up.
This isn't surprising - that statement doesn't allow for any kind of a "gradual" transition from one voltage to another, which gives the time-stepping algorithm fits. Many available versions of SPICE apparently don't even allow that kind of statement, and those that do (for example, PSPICE and LTSpice) seem to deal with that by proprietary modifications to the simulator code.
You might want to consider a note in the documentation to the effect that while it is OK syntax, it won't work properly. Or, of course, you could modify the code - but I'm sure that's not a quick task, or even a desired one.
Finally, thanks again for all your great work on Xyce!
Fred