This is a snippet of the original netlist
.OPTION
+ ARTIST=2
+ INGOLD=2
+ PARHIER=LOCAL
+ PSF=2
.subckt NOR2 a1 a2 zn vdd vss
m1 zn a2 vss vss nch l=350e-9 w=2e-6 m=1 nf=1
m0 zn a1 vss vss nch l=350e-9 w=2e-6 m=1 nf=1
m3 zn a2 net8 vdd pch l=300e-9 w=2e-6 m=2 nf=1
m2 net8 a1 vdd vdd pch l=300e-9 w=2e-6 m=2 nf=1
.ends NOR2
xi4 net23 r net38 vdd gnd NOR2
d0 net023 gnd pdio area=175e-12 m=1
xc1 vc1 gnd mimcap lt=4.79e-6 wt=4.79e-6 mf=1
And I made the following changes to run this netlist in xyce...
.PREPROCESS REPLACEGROUND TRUE
.subckt NOR2 a1 a2 zn vdd vss
m1 zn a2 vss vss nch l=350e-9 w=2e-6 m=1
m0 zn a1 vss vss nch l=350e-9 w=2e-6 m=1
m3 zn a2 net8 vdd pch l=300e-9 w=2e-6 m=2
m2 net8 a1 vdd vdd pch l=300e-9 w=2e-6 m=2
.ends
xi4 net23 r net38 vdd gnd NOR2
d0 net023 gnd pdio area=175e-12
C1 vc1 gnd 50f ;femto
In summary I...
-removed the original options (I kept temp in with the right syntax)
-removed the subcircuit name after ".ends"
-removed the nf=1 (all the transistors in the circuit have that, (I am guessing xyce might have that as default?)
-used regular capacitors instead of mimcaps (I am told that not using the mimcap model should be okay for the circuit)
Running this new netlist I am not getting the original output. But it seems I am off by a considerable amount. Did I have to write somethign in the new netlist related to the options from the previous netlist? None of the previous options seem too critical for correct operation.