Changing netlist from Cadence for xyce compatibility

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Pablo Soler Portilla

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May 24, 2019, 7:16:15 PM5/24/19
to xyce-users
This is a snippet of the original netlist

.OPTION
+    ARTIST=2
+    INGOLD=2
+    PARHIER=LOCAL
+    PSF=2


.subckt NOR2 a1 a2 zn vdd vss
m1 zn a2 vss vss nch l
=350e-9 w=2e-6 m=1 nf=1
m0 zn a1 vss vss nch l
=350e-9 w=2e-6 m=1 nf=1
m3 zn a2 net8 vdd pch l
=300e-9 w=2e-6 m=2 nf=1
m2 net8 a1 vdd vdd pch l
=300e-9 w=2e-6 m=2 nf=1
.ends NOR2


xi4 net23 r net38 vdd gnd NOR2
d0 net023 gnd pdio area
=175e-12 m=1
xc1 vc1 gnd mimcap lt=4.79e-6 wt=4.79e-6 mf=1



And I made the following changes to run this netlist in xyce...

.PREPROCESS REPLACEGROUND TRUE

.subckt NOR2 a1 a2 zn vdd vss
m1 zn a2 vss vss nch l
=350e-9 w=2e-6 m=1
m0 zn a1 vss vss nch l
=350e-9 w=2e-6 m=1
m3 zn a2 net8 vdd pch l
=300e-9 w=2e-6 m=2
m2 net8 a1 vdd vdd pch l
=300e-9 w=2e-6 m=2
.ends

xi4 net23 r net38 vdd gnd NOR2
d0 net023 gnd pdio area=175e-12
C1 vc1 gnd 50f ;femto

In summary I...

-removed the original options (I kept temp in with the right syntax)
-removed the subcircuit name after ".ends"
-removed the nf=1 (all the transistors in the circuit have that, (I am guessing xyce might have that as default?)
-used regular capacitors instead of mimcaps (I am told that not using the mimcap model should be okay for the circuit)

Running this new netlist I am not getting the original output. But it seems I am off by a considerable amount. Did I have to write somethign in the new netlist related to the options from the previous netlist?  None of the previous options seem too critical for correct operation. 

xyce-users

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May 31, 2019, 10:29:52 AM5/31/19
to xyce-users
Pablo,

The Xyce Team has been working on improving interoperability between HSPICE and Xyce netlists.  The Xyce website has an App Note on that subject at https://xyce.sandia.gov/documentation/index.html.  There will be additional improvements in the next Xyce release (6.11).  With that said, it's hard to diagnose your issue without seeing the whole netlist.

I'm not familiar with any differences between the standard SPICE C-device model and your mimcap model.  So, I can't comment on that issue.

Which MOSFET model (e.g., model level in HSPICE) is being used by your nch and pch model card?  Various simulators do use different level numbers to refer to differ MOSFET models, although that's typically not an issue between Xyce and HSPICE.

These particular HSPICE options (PSF, ARTIST and INGOLD) should not matter in Xyce.  Finally, .OPTION PARHIER=LOCAL conforms to how Xyce handles parameters defined in subcircuits.  So, commenting that out should be okay also.

--The Xyce Team

xyce-users

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May 31, 2019, 11:52:52 AM5/31/19
to xyce-users
Pablo,

One other possibility is that the default nominal temperature in HSPICE is 25C.  The default nominal temperature in Xyce is 27C.  We have seen that make a difference in some simulations, depending on the device models in the netlist.  So, you might try adding .OPTIONS DEVICE TNOM=25 to your Xyce netlist.

--The Xyce Team
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