Xyce appears to fail to recongize device binning

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John Mayega

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Nov 30, 2023, 5:32:19 AM11/30/23
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I am running Xyce on a model from Global Foundries 130BCDlite.  The models have been converted to work with Xyce.  However when the netlist calls a device with binning present i.e.  ".MODEL pmos_1p5.0 PMOS" , ".MODEL pmos_1p5.1 PMOS"
Then Xyce produces the following error:
Netlist error in file
 /home/metrio/hyphy/Libraries/HSPICE_xyce_conv/models_lv.hspice at or near
 line 1060
 Model is required for device M0 and no valid model card found.

This also occurs for the case where a device is not binned but is defined with the following syntax:
".model  nmos_1p5.0  nmos  level = 54"

In such cases changing the definition to ".model  nmos_1p5  nmos  level = 54" resolves the issue.

Thank You,
-John

xyce-users

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Nov 30, 2023, 6:55:42 PM11/30/23
to xyce-users
John,

thanks for reporting this.  Xyce (in theory) supports model binning and you can find some simple model binning tests in our test suite can be found here:  Xyce_Regression/Netlists/MODEL_BINNING.    

Without more information, it is a bit hard to see what is going wrong.    If I edit one of the simple tests (like comparatorBinning.cir) to use the same naming convention you describe, it appears to work fine.   Can you share what the device instance line looks like?

thanks,
Eric

John Mayega

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Dec 1, 2023, 5:38:27 AM12/1/23
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Hello Eric,
    Thank you for the feedback it helped me debug the issue.  So it seems there were three transistor instantiations that were producing the error. 
These were the transistors:
XMP0 N001 N001 avdd avdd pmos_1p5 W=64.0u L=1.0u NF=16 M=1
XMP2 ibias1_10uA N001 avdd avdd pmos_1p5 W=64.0u L=1.0u NF=16 M=1
XMP3 ibias2_10uA N001 avdd avdd pmos_1p5 W=64.0u L=1.0u NF=16 M=1

Xyce did not give the line which produced the error in the spice netlist so I had to go through a process of elimination to find them. (There may be a more verbose debug settings I am not aware of?)

In the binning the maximum transistor width is 50um.  However since the transistors have 16 fingers I would expect the 4um width model to be used.  When I change the transistor width to W= 50um the simulation runs correctly.

As a workaround I changed the transistor to:
XMP3 ibias2_10uA N001 avdd avdd pmos_1p5 W=32.0u L=1.0u NF=8 M=2

For your reference here are the bins used:
.model  pmos_1p5.0  pmos  level = 54
+lmin    = 1.3e-007      
+lmax    = 5e-007        
+wmin    = 1.5e-007      
+wmax    = 6e-007    
.model  pmos_1p5.1  pmos  level = 54
+lmin    = 5e-007        
+lmax    = 1e-006        
+wmin    = 1.5e-007      
+wmax    = 6e-007  
.model  pmos_1p5.2  pmos  level = 54
+lmin    = 1e-006        
+lmax    = 1e-005        
+wmin    = 1.5e-007      
+wmax    = 6e-007    
.model  pmos_1p5.3  pmos  level = 54
+lmin    = 1e-005        
+lmax    = 10.0001e-005  
+wmin    = 1.5e-007      
+wmax    = 6e-007  
.model  pmos_1p5.4  pmos  level = 54
+lmin    = 1.3e-007      
+lmax    = 5e-007        
+wmin    = 6e-007        
+wmax    = 1.2e-006  
.model  pmos_1p5.5  pmos  level = 54
+lmin    = 5e-007        
+lmax    = 1e-006        
+wmin    = 6e-007        
+wmax    = 1.2e-006  
.model  pmos_1p5.6  pmos  level = 54
+lmin    = 1e-006        
+lmax    = 1e-005        
+wmin    = 6e-007        
+wmax    = 1.2e-006  
.model  pmos_1p5.7  pmos  level = 54
+lmin    = 1e-005        
+lmax    = 10.0001e-005  
+wmin    = 6e-007        
+wmax    = 1.2e-006    
.model  pmos_1p5.8  pmos  level = 54
+lmin    = 1.3e-007      
+lmax    = 5e-007        
+wmin    = 1.2e-006      
+wmax    = 1e-005    
.model  pmos_1p5.9  pmos  level = 54
+lmin    = 5e-007        
+lmax    = 1e-006        
+wmin    = 1.2e-006      
+wmax    = 1e-005      
.model  pmos_1p5.10  pmos  level = 54
+lmin    = 1e-006        
+lmax    = 1e-005        
+wmin    = 1.2e-006      
+wmax    = 1e-005        
.model  pmos_1p5.11  pmos  level = 54
+lmin    = 1e-005        
+lmax    = 10.0001e-005  
+wmin    = 1.2e-006      
+wmax    = 1e-005  
.model  pmos_1p5.12  pmos  level = 54
+lmin    = 1.3e-007      
+lmax    = 5e-007        
+wmin    = 1e-005        
+wmax    = 50.001e-6      
.model  pmos_1p5.13  pmos  level = 54
+lmin    = 5e-007        
+lmax    = 1e-006        
+wmin    = 1e-005        
+wmax    = 50.001e-6  
.model  pmos_1p5.14  pmos  level = 54
+lmin    = 1e-006        
+lmax    = 1e-005        
+wmin    = 1e-005        
+wmax    = 50.001e-6  
.model  pmos_1p5.15  pmos  level = 54
+lmin    = 1e-005        
+lmax    = 10.0001e-005  
+wmin    = 1e-005        
+wmax    = 50.001e-6  

xyce-users

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Dec 3, 2023, 7:02:20 PM12/3/23
to xyce-users

Hi John,

Currently, Xyce's binning is strict, in that if a MOSFET instance specifies L,W parameters that are outside the mins and maxes of all the bins, it will fail with a fatal error.

At least one other user has pointed out to us that it would be better for binning to simply select the best match.   So, if L,W are inside a bin, use that one, but if they are outside all the bins, then select the one that is closest.  This is a reasonable thing to do, but I haven't had time to do this yet.  So, for now,  you'll either have to modify the L and/or W of any instances that cause this type of error, or you'll have to modify at least one of the bins to have a larger range.

thanks,
Eric

Mehmet Cirit

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Dec 3, 2023, 9:45:52 PM12/3/23
to xyce-users
On this issue, I also noticed a practice of specifying a catch-all bin, which accommodates
all bin failures.

.model n.global nmos ( ... )

will catch all bin failures. I think the closest bin is a more reasonable choice, but for being compatible
with other simulators, it may make sense to have both methods.

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