SR latch basic simulation error-timestep error with pulses, SR latch

[pablo_sole...@brown.edu]

I am trying to simulate an SR latch with pulses. Though I've tried changing several parameters to see reasonable values but cannot see the correct behavior for the SR latch.  I am having trouble with

-setting the pulses so they dont cause a timestep issue.  I want to have a Set pulse with 20ns rise time ,40ns high, 20ns fall time and after about 50ns another Reset pulse

-seeing correct behavior from SR latch once the pulses work.  When I have pulses on I am not getting behavior I expect

I set constant values for voltage inputs to see if I could narrow down the issue in the SR latch, but ran into another timestep issue. Could someone let me know where I am going wrong setting up this SR latch to work? 

Unit Test for 2-input NOR Digital Device-SR latch

.options timeint reltol=1.0e-3

.tran 1ns 2us

* Sources

.param V_LO=0 V_REF=0 V_HI=10

;V1 5 0  PULSE ({V_LO} {V_HI} 20ns 20ns 20ns 40ns 250ns) ;SET

;V2 4 0  PULSE ({V_LO} {V_HI} 150ns 20ns 20ns 40ns 250ns) ;RESET

V1 5 0  {V_LO};set

V2 4 0  {V_LO};reset

;first prn with 5 high / 4 low -> v(9) low, v(10) high

;second prn with 5 low / 4 high -> v(9) high, v(10) low

;third prn with 5 low / 4 low ->

* Output

.print tran PRECISION=4 WIDTH=10 v(5) v(4) v(9) v(10) ; S R Q Q'  ?

* Set SR Latch default parameters:

.param R1HI=5 R1LO=200 R0HI=200 R0LO=5 RIN=1000 R1=100

.param SW=5.e-9  CAPOUT=1.e-12  CAPIN=1.e-12

* Digital power node

Vdd 1 0 10V

U1 NOR(2) 1 0   5 10  9 DMOD

U2 NOR(2) 1 0   4 9  10 DMOD

;R1 9 0 100K

.model DMOD DIG ( CLO=CAPOUT  CHI=CAPOUT

+ S0RLO=R0LO  S0RHI=R0HI  S0TSW=SW

+ S0VLO=0  S0VHI=2

+ S1RLO=R1LO  S1RHI=R1HI  S1TSW=SW

+ S1VLO=8  S1VHI=12

+ RLOAD=RIN   CLOAD=CAPIN

+ DELAY=20ns )

.end

[xyce-users]

Hello, sorry I didn't reply more quickly.

I just tried running your circuit.  The first thing to be aware of is that it isn't even successfully passing the DCOP calculation.  So, assuming that your build of Xyce is behaving the same as mine, you are not getting a time step failure.  You aren't even getting to the time stepping phase of the calculation, so time integration options won't help, and change to the pulses aren't likely to help either, unless you are just changing the initial DC value.

I'm not sure why (yet) the circuit is failing the DCOP.   The Newton solver is failing to make progress, and other DC methods like gmin stepping aren't helping either.  If I comment one  or the other NOR gate out of the circuit it runs fine.  I attempted adding some RC components in between the NOR gates but that didn't seem to help.

So, I'll enter a bug on this issue.  The digital devices are Xyce have never worked that well, and you may have uncovered another example of this.  In the meantime if you want behavioral NOR gates and latches you might consider creating them via subcircuits and expressions.  That approach probably has a better chance of success.

thanks,

the Xyce team

[xyce-users]

Hello again,

I quickly threw together a circuit similar to yours, which does run.  Unlike your version, however, I did not use the "U" device with the NOR option.  Instead, I created a behavioral NOR gate and a behavioral NORLATCH subcircuit based on the switch device.   

Unit Test for NOR-basd latch, using the switch device

.options timeint reltol=1.0e-3
.tran 1ns 2us

* Sources
.param V_LO=0 V_REF=0 V_HI=10

V1 s 0  PULSE ({V_LO} {V_HI} 20ns 20ns 20ns 40ns 250ns) ;SET
V2 r 0  PULSE ({V_LO} {V_HI} 150ns 20ns 20ns 40ns 250ns) ;RESET
*V1 s 0  {V_LO};set
*V2 r 0  {V_LO};reset

*first prn with 5 high / 4 low -> v(9) low, v(10) high
*second prn with 5 low / 4 high -> v(9) high, v(10) low
*third prn with 5 low / 4 low ->

* Output
.print tran v(s) v(r) v(q) v(qp)
* S R Q QP

* Set SR Latch default parameters:
.param R1HI=5 R1LO=200 R0HI=200 R0LO=5 RIN=1000 R1=100
.param SW=5.e-9  CAPOUT=1.e-12  CAPIN=1.e-12


* Digital power node

Vdd 10 0 10V

.param Rstd=1MEG
.param Cstd=0.01pf
XLATCH1 s r q qp 10 NORLATCH
Rq q 0 {Rstd}
Rqp qp 0 {Rstd}



* NOR-LATCH subcircuit
*  S R Q QP VCC
.subckt norlatch S R Q QP VCC

XNOR1 S Q2 QP VCC NOR
R1  QP QP2 {Rstd}
C1  QP2 0  {Cstd}

XNOR2 R QP2 Q VCC NOR
R2  Q Q2 {Rstd}
C2  Q2 0 {Cstd}
.ends


.SUBCKT NOR 1 2 3 4
* TERMINALS A B OUT VCC
RL 3 4 500
S1 3 0 1 0  SW
S2 3 0 2 0  SW
.ENDS

.MODEL SW VSWITCH(VON=2.6 VOFF=2.4 RON=10 ROFF=1MEG)


.end