PWL Delay Appears to Cause Time step too small Error

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John Mayega

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Dec 21, 2023, 9:58:03 AM12/21/23
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Hello,
   I am using the delay option to delay the PWL output as specified in the Reference Guide:
PWL T0 V0 [Tn Vn]*
PWL FILE "<name>" [TD=<timeDelay>] [R=<repeatTime>]

When increasing the TD value to beyond the transient simulation time no error occurs.

Here is my spice netlist
-----------------------------------------------------------------
**.subckt tb_pwl
VV4 softrst VSS pwl(0 1.5 1.0u 1.5 1.001u 0 ) TD=50u
C1 softrst VSS 1p m=1
v3 VSS GND dc 0 ac 0
**.ends
.GLOBAL GND

.PREPROCESS REPLACEGROUND TRUE
.PREPROCESS REMOVEUNUSED C,D,M
.PREPROCESS ADDRESISTORS NODCPATH 1G

.tran 1n 100u uic

.PRINT TRAN FORMAT=RAW  v(*)

.end
-----------------------------------------------------------------

I get the following error:
 *** Transient failure history:
Time        Time      Step   EstErr       Non-Linear Solver       node     node
(sec)       Step     Status  OverTol    Status    Iters  ||F||    index    name
 5.000e-05  2.156e-13  fail  7.776e+05  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  5.390e-14  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  1.078e-13  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  5.390e-14  fail  3.093e+06  P:sm nrm   2  0.000e+00     -1    N/A
 5.000e-05  1.347e-14  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  2.695e-14  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  1.347e-14  fail  1.237e+07  P:sm nrm   2  0.000e+00     -1    N/A
 5.000e-05  3.369e-15  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  6.737e-15  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  3.369e-15  fail  4.948e+07  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  8.421e-16  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  1.684e-15  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  8.421e-16  fail  1.979e+08  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  2.105e-16  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  4.211e-16  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  2.105e-16  fail  7.916e+08  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  5.263e-17  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  1.053e-16  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  5.263e-17  fail  3.167e+09  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  1.316e-17  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  2.632e-17  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  1.316e-17  fail  1.267e+10  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  3.290e-18  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  6.580e-18  pass  0.000e+00  P:sm nrm   1  0.000e+00     -1    N/A
 5.000e-05  3.286e-18  fail  5.068e+10  P:sm nrm   2  0.000e+00     -1    N/A
Time step too small near step number: 57  Exiting transient loop.


***** Solution Summary *****
Number Successful Steps Taken: 57
Number Failed Steps Attempted: 21
Number Jacobians Evaluated: 81
Number Linear Solves: 81
Number Failed Linear Solves: 0
Number Residual Evaluations: 159
Number Nonlinear Convergence Failures: 0
Total Residual Load Time: 0.000 seconds
Total Jacobian Load Time: 0.000 seconds
Total Linear Solution Time: 0.000 seconds


***** Total Simulation Solvers Run Time: 0.004 seconds
***** Total Elapsed Run Time:            0.008 seconds
*****
***** End of Xyce(TM) Simulation
*****

Timing summary of 1 processor
                 Stats                   Count       CPU Time              Wall Time
---------------------------------------- ----- --------------------- ---------------------
Xyce                                         1        0.003 (100.0%)        0.008 (100.0%)
  Analysis                                   1        0.002 (59.32%)        0.004 (49.36%)
    Transient                                1        0.002 (59.28%)        0.004 (49.29%)
      Nonlinear Solve                       78        0.001 (32.95%)        0.002 (20.06%)
        Residual                           159        0.000 ( 9.59%)        0.000 ( 6.12%)
        Jacobian                            81        0.000 ( 2.74%)        0.000 ( 1.75%)
        Linear Solve                        81        0.000 ( 8.14%)        0.000 ( 4.29%)
      Successful Step                       57        0.000 ( 5.25%)        0.000 ( 3.11%)
      Failed Steps                          21        0.000 ( 6.96%)        0.000 ( 3.50%)
  Netlist Import                             1        0.000 (12.44%)        0.002 (19.52%)
    Parse Context                            1        0.000 ( 6.24%)        0.000 ( 3.32%)
    Distribute Devices                       1        0.000 ( 0.00%)        0.000 ( 4.30%)
    Verify Devices                           1        0.000 ( 0.00%)        0.000 ( 0.09%)
    Instantiate                              1        0.000 ( 2.51%)        0.000 ( 1.42%)
  Late Initialization                        1        0.000 ( 0.23%)        0.001 (10.11%)
    Global Indices                           1        0.000 ( 0.00%)        0.000 ( 0.98%)
  Setup Matrix Structure                     1        0.000 ( 0.00%)        0.000 ( 1.30%)

xyce-users

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Dec 24, 2023, 2:09:09 PM12/24/23
to xyce-users

Hello,

I just reproduced your error.  It looks like there may be an issue with PWL sources when the TD parameter is set.

if I replace your  line:
VV4 softrst VSS pwl(0 1.5 1.0u 1.5 1.001u 0 ) TD=50u

with the (in theory) equivalent line:

VV4 softrst VSS pwl( 0.0 0.0 50u 1.5 51.0u 1.5 51.001u 0 )

it then  runs without any trouble.    

In the TD case (your circuit), it bombs when it gets to time=TD.    I am guessing there  is a breakpointing problem in the TD case. 

I'll open an issue about this on our internal tracker.  

thanks,
Eric

John Mayega

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Jan 18, 2024, 6:22:33 AMJan 18
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Thank You for the fix.

Regards,
-John
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