Sampling does not appear to support mismatch

[John Mayega]

Hello,

    I have been running the .sampling functionality to simulate mis-match in my circuit.  I am using an industry library from global foundries that has been converted for use with Xyce.  The statistical behavior is enabled in the model with switches.  I am able to see the global variation when its is enabled.  However when mismatch is enabled no variation is present.  

I am using the following settings for the simulation:
.SAMPLING type=normal useExpr=true
.options SAMPLES numsamples=20 OUTPUTS={v(nmos)},{v(res1k)},{v(res2)}
+ SAMPLE_TYPE=LHS stdoutput=true SEED=123456789

Thank You

[xyce-users]

Hello,

You are correct that Xyce doesn't support local variation, or at least doesn't support the  standard shorthand for specifying it used by tools like Hspice.

I implemented the expression-based sampling in Xyce a couple of years ago, and unfortunately, at the time I was unaware of the convention.  I had originally implemented sampling and other UQ methods as part of a research project, and in the initial implementation they weren't connected to expression operators like AGAUSS at all.  That came a bit later. 

We do have an internal issue for this mistake in our issue-tracker, and I don't think it would be very hard to fix.

I think for your issue, you expect that if you specify something like:

.param resval=aunif(1000,400)

r_one 1 2 resval

r_two 2 3 resval

r_three 3 4 resval

in this case all 3 resistors will get unique random values.  In Xyce currently, the parameter resval is given a single random number and this is applied to all 3 resistors.  So they are locked together.  One possible workaround is to specify it like this:

r_one 1 2 aunif(1000,400)

r_two 2 3 aunif(1000,400)

r_three 3 4 aunif(1000,400)

then each resistor would get its own random number, which is what you want.  That probably isn't an easy workaround in a modern PDK, I am guessing.  But that would produce the behavior you want.

My understanding is that Xyce's current behavior is expected in other simulators only if there is an extra layer of indirection.    For example:

.param resval=aunif(1000,400)

.param res2=resval

r_one 1 2 res2

r_two 2 3 res2

r_three 3 4 res2

would cause the 3 resistors to be locked together in most simulators, since "resval" is hidden behind "res2".

Anyway, like I said, this is in our issue tracker and I'll try to fix it soon.

thanks,

Eric

[xyce-users]

Hello, I wanted to let you know that this issue has been fixed in Xyce. The fix is in our internal repository as of today.   It will be in our public git repository the next time we sync up.  Also the fix will be in our next formal code release.

thanks,

Eric

[John Mayega]

Thank You.  Looking forward to the update.

[John Mayega]

Hello,

   Once again thank you for the feature.  I was just wondering if you had an idea when the next formal code release might be?

Thanks Again,

-John

[xyce-users]

Xyce 7.7 is scheduled to be released in mid-May, so just a month away. Our typical release schedule is every six months, in May and November.