While the syntax on that line is supposedly acceptable according to the Verilog-A 2.4 standard, ADMS does not recognize an attempt to initialize a variable on the same line as the declaration. This is a limitation of ADMS itself, not of Xyce's use of ADMS.
Line 54, which is commented out in the version you have posted here, declares a variable "a0" and attempts to assign a value to it on the same line. This is not recognized by ADMS.
There is another instance of the same thing on line 70, where "real p = 10;" appears.
If you break up these lines into a strict declaration (e.g. "real a0;" and "real p;") and move the assignment of a value elsewhere, the module gets past both problems. In the case of the "a0" assignment, putting it inside the "initial_step" block is reasonable. For the "p" assignment, put the assignment of value after the "begin" line of the analog function.
There are other problems with this module, though, including use of a flow probe in a manner not currently supported by Xyce/ADMS.