This mostly about finding a starting point where we can do minimal work to get something useful, if you have models you would like to use but are not currently supported that would be helpful.
The pluggable-parser idea would support parsers that just do minor tweaks to existing netlists for (say) LtSpice, SIMPLIS etc., and could just be in Perl/Python - basically like the C preprocessor. Goal is to have it as something people can hack to their own needs and not have to rely on the Sandia team.
Can probably do Verilog to U model too.
I can do coding, but I usually don't have any good design data to work with.